DS891 Datasheet, PDF (14/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Xilinx Memory Protection Unit (XMPU)
• Region based memory protection unit
• Up to 16 regions
• Each region supports address alignment of 1MB or 4KB
• Regions can overlap; the higher region number has priority
• Each region can be independently enabled or disabled
• Each region has a start and end address
Graphics Processing Unit (GPU)
• Supports OpenGL ES 1.1 & 2.0
• Supports OpenVG 1.1
• Operating target frequency: up to 667MHz
• Single Geometry Processor and two Pixel processor
• Pixel Fill Rate: 2 Mpixel/sec/MHz
• Triangle Rate: 0.11 Mtriangles/sec/MHz
• 64KB Level 2 Cache (read-only)
• 4X and 16X Anti-aliasing Support
• ETC1 texture compression to reduce external memory bandwidth
• Extensive texture format support
o RGBA 8888, 565, 1556
o Mono 8, 16
o YUV format support
• Automatic load balancing across different graphics shader engines
• 2D and 3D graphic acceleration
• Up to 4K texture input and 4K render output resolutions
• Each geometry processor and pixel processor supports 4KB page MMU
• Power island gating on each GPU engine and shared cache
• Optional eFUSE disable
Dynamic Memory Controller (DDRC)
• DDR3, DDR3L, DDR4, LPDDR3, LPDDR4
• Target data rate: Up to 2400Mb/s DDR4 operation in -1 speed grade
• 32-bit and 64-bit bus width support for DDR4, DDR3, DDR3L, or LPDDR3 memories, and 32-bit bus width
support for LPDDR4 memory
• ECC support (using extra bits)
• Up to a total DRAM capacity of 32GB
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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