DS891 Datasheet, PDF (12/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Processing System
Application Processing Unit (APU)
The key features of the APU include:
• 64-bit quad-core ARM Cortex-A53 MPCores. Features associated with each core include:
o ARM v8-A Architecture
o Operating target frequency: up to 1.5GHz
o Single and double precision floating point:
4 SP / 2 DP FLOPs
o NEON Advanced SIMD support with single and double precision floating point instructions
o A64 instruction set in 64-bit operating mode, A32/T32 instruction set in 32-bit operating mode
o Level 1 cache (separate instruction and data, 32KB each for each Cortex-A53 CPU)
– 2-way set-associative Instruction Cache with parity support
– 4-way set-associative Data Cache with ECC support
o Integrated memory management unit (MMU) per processor core
o TrustZone for secure mode operation
o Virtualization support
• Ability to operate in single processor, symmetric quad processor, and asymmetric quad-processor modes
• Integrated 16-way set-associative 1MB Unified Level 2 cache with ECC support
• Interrupts and Timers
o Generic interrupt controller (GIC-400)
o ARM generic timers (4 timers per CPU)
o One watchdog timer (WDT)
o One global timer
o Two triple timers/counters (TTC)
• Little and big endian support
o Big endian support in BE8 mode
• CoreSight debug and trace support
o Embedded Trace Macrocell (ETM) for instruction trace
o Cross trigger interface (CTI) enabling hardware breakpoints and triggers
• ACP interface to PL for I/O coherency and Level 2 cache allocation
• ACE interface to PL for full coherency
• Power island gating on each processor core
• Optional eFUSE disable per core
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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