DS891 Datasheet, PDF (18/41 Pages) Xilinx, Inc – Zynq UltraScale+ MPSoC Overview

Zynq UltraScale+ MPSoC Overview
Configuration Security Unit (CSU)
• Triple redundant Secure Processor Block (SPB) with built-in ECC
• Crypto Interface Block consisting of
o 256-bit AES-GCM
o SHA-3/384
o 4096-bit RSA
• Key Management Unit
• Built-in DMA
• PCAP interface
• Supports ROM validation during pre-configuration stage
• Loads First Stage Boot Loader (FSBL) into OCM in either secure or non-secure boot modes
• Supports voltage, temperature, and frequency monitoring after configuration
Xilinx Peripheral Protection Unit (XPPU)
• Provides peripheral protection support
• Up to 20 masters simultaneously
• Multiple aperture sizes
• Access control for a specified set of address apertures on a per master basis
• 64KB peripheral apertures and controls access on per peripheral basis
I/O Peripherals
The IOP unit contains the data communication peripherals. Key features of the IOP include:
Triple-Speed Gigabit Ethernet
• Compatible with IEEE Std 802.3 and supports 10/100/1000Mb/s transfer rates (Full and Half duplex)
• Supports jumbo frames
• Built-in Scatter-Gather DMA capability
• Statistics counter registers for RMON/MIB
• Multiple I/O types (1.8, 2.5, 3.3V) on RGMII interface with external PHY
• GMII interface to PL to support interfaces as: TBI, SGMII, and RGMII v2.0 support
• Automatic pad and cyclic redundancy check (CRC) generation on transmitted frames
• Transmitter and Receive IP, TCP, and UDP checksum offload
• MDIO interface for physical layer management
DS891 (v1.3) September 23, 2016
www.xilinx.com
Advance Product Specification
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