LM3S101 Datasheet, PDF (81/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S101 Microcontroller
3.1.3
System Control Block (SCB)
The System Control Block (SCB) provides system implementation information and system control,
including configuration, control, and reporting of the system exceptions.
3.2 Register Map
Table 3-2 on page 81 lists the Cortex-M3 Peripheral SysTick, NVIC and SCB registers. The offset
listed is a hexadecimal increment to the register's address, relative to the Core Peripherals base
address of 0xE000.E000.
Note: Register spaces that are not used are reserved for future or internal use. Software should
not modify any reserved memory address.
Table 3-2. Peripherals Register Map
Offset Name
Type
Reset
Description
System Timer (SysTick) Registers
0x010 STCTRL
R/W
0x0000.0000
0x014 STRELOAD
R/W
0x0000.0000
0x018 STCURRENT
R/WC
0x0000.0000
Nested Vectored Interrupt Controller (NVIC) Registers
0x100 EN0
R/W
0x0000.0000
0x180 DIS0
R/W
0x0000.0000
0x200 PEND0
R/W
0x0000.0000
0x280 UNPEND0
R/W
0x0000.0000
0x300 ACTIVE0
RO
0x0000.0000
0x400 PRI0
R/W
0x0000.0000
0x404 PRI1
R/W
0x0000.0000
0x408 PRI2
R/W
0x0000.0000
0x40C PRI3
R/W
0x0000.0000
0x410 PRI4
R/W
0x0000.0000
0x414 PRI5
R/W
0x0000.0000
0x418 PRI6
R/W
0x0000.0000
0x41C PRI7
R/W
0x0000.0000
0xF00 SWTRIG
WO
0x0000.0000
System Control Block (SCB) Registers
0xD00 CPUID
RO
0x410F.C231
0xD04 INTCTRL
R/W
0x0000.0000
0xD08 VTABLE
R/W
0x0000.0000
SysTick Control and Status Register
SysTick Reload Value Register
SysTick Current Value Register
Interrupt 0-29 Set Enable
Interrupt 0-29 Clear Enable
Interrupt 0-29 Set Pending
Interrupt 0-29 Clear Pending
Interrupt 0-29 Active Bit
Interrupt 0-3 Priority
Interrupt 4-7 Priority
Interrupt 8-11 Priority
Interrupt 12-15 Priority
Interrupt 16-19 Priority
Interrupt 20-23 Priority
Interrupt 24-27 Priority
Interrupt 28-29 Priority
Software Trigger Interrupt
CPU ID Base
Interrupt Control and State
Vector Table Offset
See
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July 14, 2014
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Texas Instruments-Production Data