LM3S101 Datasheet, PDF (43/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S101 Microcontroller
Table 2-2. Processor Register Map (continued)
Offset Name
Type
Reset
Description
-
R4
-
R5
-
R6
-
R7
-
R8
-
R9
-
R10
-
R11
-
R12
-
SP
-
LR
-
PC
-
PSR
-
PRIMASK
-
FAULTMASK
-
BASEPRI
-
CONTROL
R/W
-
Cortex General-Purpose Register 4
R/W
-
Cortex General-Purpose Register 5
R/W
-
Cortex General-Purpose Register 6
R/W
-
Cortex General-Purpose Register 7
R/W
-
Cortex General-Purpose Register 8
R/W
-
Cortex General-Purpose Register 9
R/W
-
Cortex General-Purpose Register 10
R/W
-
Cortex General-Purpose Register 11
R/W
-
Cortex General-Purpose Register 12
R/W
-
Stack Pointer
R/W
0xFFFF.FFFF Link Register
R/W
-
Program Counter
R/W
0x0100.0000 Program Status Register
R/W
0x0000.0000 Priority Mask Register
R/W
0x0000.0000 Fault Mask Register
R/W
0x0000.0000 Base Priority Mask Register
R/W
0x0000.0000 Control Register
See
page
44
44
44
44
44
44
44
44
44
45
46
47
48
52
53
54
55
2.3.4
Register Descriptions
This section lists and describes the Cortex-M3 registers, in the order shown in Figure 2-3 on page 42.
The core registers are not memory mapped and are accessed by register name rather than offset.
Note: The register type shown in the register descriptions refers to type during program execution
in Thread mode and Handler mode. Debug access can differ.
July 14, 2014
43
Texas Instruments-Production Data