LM3S101 Datasheet, PDF (393/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S101 Microcontroller
14 Signal Tables
Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7
and PC[3:0]) which default to the JTAG functionality.
The following tables list the signals available for each pin. Functionality is enabled by software with
the GPIOAFSEL register. All digital inputs are Schmitt triggered.
■ Signals by Pin Number
■ Signals by Signal Name
■ Signals by Function, Except for GPIO
■ GPIO Pins and Alternate Functions
■ Connections for Unused Signals
Important: The 28-pin SOIC package is OBSOLETE. TI has discontinued production of this device.
14.1 28-Pin SOIC Package Pin Tables
14.1.1 Signals by Pin Number
Table 14-1. Signals by Pin Number
Pin Number
1
2
3
4
5
6
Pin Name
PB7
TRST
PB6
C0+
PB5
C0o
C1-
PB4
C0-
RST
LDO
Pin Type
I/O
I
I/O
I
I/O
O
I
I/O
I
I
-
7
VDD
-
8
GND
-
9
OSC0
I
10
OSC1
O
PA0
I/O
11
U0Rx
I
PA1
I/O
12
U0Tx
O
PA2
I/O
13
SSIClk
I/O
Buffer Type^a Description
TTL
GPIO port B bit 7.
TTL
JTAG TRST.
TTL
GPIO port B bit 6.
Analog Analog comparator 0 positive input.
TTL
GPIO port B bit 5.
TTL
Analog comparator 0 output.
Analog Analog comparator 1 negative input.
TTL
GPIO port B bit 4.
Analog Analog comparator 0 negative input.
TTL
System reset input.
Power
Low drop-out regulator output voltage. This pin requires an external
capacitor between the pin and GND of 1 µF or greater.
Power Positive supply for I/O and some logic.
Power Ground reference for logic and I/O pins.
Analog Main oscillator crystal input or an external clock reference input.
Analog
Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
TTL
GPIO port A bit 0.
TTL
UART module 0 receive.
TTL
GPIO port A bit 1.
TTL
UART module 0 transmit.
TTL
GPIO port A bit 2.
TTL
SSI clock.
July 14, 2014
393
Texas Instruments-Production Data