LM3S101 Datasheet, PDF (71/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S101 Microcontroller
2.5.7.2
2.6
2.6.1
Exception Return
Exception return occurs when the processor is in Handler mode and executes one of the following
instructions to load the EXC_RETURN value into the PC:
■ An LDM or POP instruction that loads the PC
■ A BX instruction using any register
■ An LDR instruction with the PC as the destination
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies
on this value to detect when the processor has completed an exception handler. The lowest four
bits of this value provide information on the return stack and processor mode. Table 2-10 on page 71
shows the EXC_RETURN values with a description of the exception return behavior.
EXC_RETURN bits 31:4 are all set. When this value is loaded into the PC, it indicates to the processor
that the exception is complete, and the processor initiates the appropriate exception return sequence.
Table 2-10. Exception Return Behavior
EXC_RETURN[31:0]
0xFFFF.FFF0
0xFFFF.FFF1
0xFFFF.FFF2 - 0xFFFF.FFF8
0xFFFF.FFF9
0xFFFF.FFFA - 0xFFFF.FFFC
0xFFFF.FFFD
0xFFFF.FFFE - 0xFFFF.FFFF
Description
Reserved
Return to Handler mode.
Exception return uses state from MSP.
Execution uses MSP after return.
Reserved
Return to Thread mode.
Exception return uses state from MSP.
Execution uses MSP after return.
Reserved
Return to Thread mode.
Exception return uses state from PSP.
Execution uses PSP after return.
Reserved
Fault Handling
Faults are a subset of the exceptions (see “Exception Model” on page 63). The following conditions
generate a fault:
■ A bus error on an instruction fetch or vector table load or a data access.
■ An internally detected error such as an undefined instruction or an attempt to change state with
a BX instruction.
■ Attempting to execute an instruction from a memory region marked as Non-Executable (XN).
Fault Types
Table 2-11 on page 72 shows the types of fault, the handler used for the fault, the corresponding
fault status register, and the register bit that indicates the fault has occurred. See page 113 for more
information about the fault status registers.
July 14, 2014
71
Texas Instruments-Production Data