LM3S101 Datasheet, PDF (258/445 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Timers
Register 4: GPTM Control (GPTMCTL), offset 0x00C
This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer
configuration, and to enable other features such as timer stall.
GPTM Control (GPTMCTL)
Timer0 base: 0x4003.0000
Timer1 base: 0x4003.1000
Offset 0x00C
Type R/W, reset 0x0000.0000
31
30
29
28
Type RO
RO
RO
RO
Reset
0
0
0
0
15
14
reserved TBPWML
Type RO
R/W
Reset
0
0
13
12
reserved
RO
RO
0
0
27
26
25
24
23
22
21
20
reserved
RO
RO
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
0
0
11
10
TBEVENT
R/W
R/W
0
0
9
8
7
6
5
4
TBSTALL TBEN reserved TAPWML reserved RTCEN
R/W
R/W
RO
R/W
RO
R/W
0
0
0
0
0
0
19
18
17
16
RO
RO
RO
RO
0
0
0
0
3
2
TAEVENT
R/W
R/W
0
0
1
0
TASTALL TAEN
R/W
R/W
0
0
Bit/Field
31:15
14
Name
reserved
TBPWML
Type
RO
R/W
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM TimerB PWM Output Level
The TBPWML values are defined as follows:
Value Description
0 Output is unaffected.
1 Output is inverted.
13:12
11:10
reserved
TBEVENT
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W
0x0
GPTM TimerB Event Mode
The TBEVENT values are defined as follows:
Value Description
0x0 Positive edge
0x1 Negative edge
0x2 Reserved
0x3 Both edges
258
July 14, 2014
Texas Instruments-Production Data