LM3S101 Datasheet, PDF (162/445 Pages) List of Unclassifed Manufacturers – Microcontroller

System Control
Register 15: Device Capabilities 1 (DC1), offset 0x010
This register provides a list of features available in the system. The Stellaris family uses this register
format to indicate the availability of the following family features in the specific device: PWM, ADC,
Watchdog timer, and debug capabilities. This register also indicates the maximum clock frequency
and maximum ADC sample rate. The format of this register is consistent with the RCGC0, SCGC0,
and DCGC0 clock control registers and the SRCR0 software reset control register.
Device Capabilities 1 (DC1)
Base 0x400F.E000
Offset 0x010
Type RO, reset 0x0000.901F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MINSYSDIV
reserved
PLL
WDT
SWO
SWD
JTAG
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
1
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
Bit/Field
31:16
15:12
Name
reserved
MINSYSDIV
Type
RO
RO
Reset
0
0x9
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
System Clock Divider
Minimum 4-bit divider value for system clock. The reset value is
hardware-dependent. See the RCC register for how to change the
system clock divisor using the SYSDIV bit.
Value Description
0x9 Specifies a 20-MHz clock with a PLL divider of 10.
11:5
reserved
RO
0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
4
PLL
RO
1
PLL Present
When set, indicates that the on-chip Phase Locked Loop (PLL) is
present.
3
WDT
RO
1
Watchdog Timer Present
When set, indicates that a watchdog timer is present.
2
SWO
RO
1
SWO Trace Port Present
When set, indicates that the Serial Wire Output (SWO) trace port is
present.
1
SWD
RO
1
SWD Present
When set, indicates that the Serial Wire Debugger (SWD) is present.
0
JTAG
RO
1
JTAG Present
When set, indicates that the JTAG debugger interface is present.
162
July 14, 2014
Texas Instruments-Production Data