LM3S101 Datasheet, PDF (251/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S101 Microcontroller
8.4.6
8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled).
In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM
Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained
by reading the GPTM Timern (GPTMTnR) register.
In Input Edge Timing mode, the timer continues running after an edge event has been detected,
but the timer interval can be changed at any time by writing the GPTMTnILR register. The change
takes effect at the next cycle after the write.
16-Bit PWM Mode
A timer is configured to PWM mode using the following sequence:
1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes.
2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4.
3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to
0x0, and the TnMR field to 0x2.
4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnPWML field
of the GPTM Control (GPTMCTL) register.
5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register.
6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value.
7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin
generation of the output PWM signal.
In PWM Timing mode, the timer continues running after the PWM signal has been generated. The
PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes
effect at the next cycle after the write.
8.5 Register Map
Table 8-5 on page 251 lists the GPTM registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that timer’s base address:
■ Timer0: 0x4003.0000
■ Timer1: 0x4003.1000
Note that the Timer module clock must be enabled before the registers can be programmed (see
page 169). There must be a delay of 3 system clocks after the Timer module clock is enabled before
any Timer module registers are accessed.
Table 8-5. Timers Register Map
Offset Name
Type
0x000 GPTMCFG
R/W
0x004 GPTMTAMR
R/W
0x008 GPTMTBMR
R/W
Reset
0x0000.0000
0x0000.0000
0x0000.0000
Description
GPTM Configuration
GPTM TimerA Mode
GPTM TimerB Mode
See
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July 14, 2014
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Texas Instruments-Production Data