LM3S101 Datasheet, PDF (117/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S101 Microcontroller
Bit/Field
8
7
6:1
0
Name
IBUS
MMARV
reserved
IERR
Type
R/W1C
R/W1C
RO
R/W1C
Reset
0
0
0
0
Description
Instruction Bus Error
Value Description
0 An instruction bus error has not occurred.
1 An instruction bus error has occurred.
The processor detects the instruction bus error on prefetching an
instruction, but sets this bit only if it attempts to issue the faulting
instruction.
When this bit is set, a fault address is not written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
Memory Management Fault Address Register Valid
Value Description
0 The value in the Memory Management Fault Address
(MMADDR) register is not a valid fault address.
1 The MMADDR register is holding a valid fault address.
If a memory management fault occurs and is escalated to a hard fault
because of priority, the hard fault handler must clear this bit. This action
prevents problems if returning to a stacked active memory management
fault handler whose MMADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Instruction Access Violation
Value Description
0 An instruction access violation has not occurred.
1 The processor attempted an instruction fetch from a location
that does not permit execution.
This fault occurs on any access to an XN region.
When this bit is set, the PC value stacked for the exception return points
to the faulting instruction and the address of the attempted access is
not written to the MMADDR register.
This bit is cleared by writing a 1 to it.
July 14, 2014
117
Texas Instruments-Production Data