LM3S101 Datasheet, PDF (143/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S101 Microcontroller
Table 5-6. System Control Register Map (continued)
Offset Name
Type
Reset
Description
0x050 RIS
0x054 IMC
0x058 MISC
0x05C RESC
0x060 RCC
0x064 PLLCFG
0x100 RCGC0
0x104 RCGC1
0x108 RCGC2
0x110 SCGC0
0x114 SCGC1
0x118 SCGC2
0x120 DCGC0
0x124 DCGC1
0x128 DCGC2
0x144 DSLPCLKCFG
0x150 CLKVCLR
0x160 LDOARST
RO
R/W
R/W1C
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0000.0000
0x0000.0000
0x0000.0000
-
0x0780.3AC0
-
0x00000040
0x00000000
0x00000000
0x00000040
0x00000000
0x00000000
0x00000040
0x00000000
0x00000000
0x0780.0000
0x0000.0000
0x0000.0000
Raw Interrupt Status
Interrupt Mask Control
Masked Interrupt Status and Clear
Reset Cause
Run-Mode Clock Configuration
XTAL to PLL Translation
Run Mode Clock Gating Control Register 0
Run Mode Clock Gating Control Register 1
Run Mode Clock Gating Control Register 2
Sleep Mode Clock Gating Control Register 0
Sleep Mode Clock Gating Control Register 1
Sleep Mode Clock Gating Control Register 2
Deep Sleep Mode Clock Gating Control Register 0
Deep Sleep Mode Clock Gating Control Register 1
Deep Sleep Mode Clock Gating Control Register 2
Deep Sleep Clock Configuration
Clock Verification Clear
Allow Unregulated LDO to Reset the Part
5.5 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
See
page
148
149
150
151
152
155
166
169
175
167
171
176
168
173
177
156
157
158
July 14, 2014
143
Texas Instruments-Production Data