LM3S101 Datasheet, PDF (10/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 4-1.
Table 4-2.
Table 4-3.
Table 4-4.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 6-1.
Table 6-2.
Table 7-1.
Table 7-2.
Table 7-3.
Table 7-4.
Table 7-5.
Table 7-6.
Table 7-7.
Table 7-8.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Table 9-1.
Table 10-1.
Revision History .................................................................................................. 17
Documentation Conventions ................................................................................ 22
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 42
Processor Register Map ....................................................................................... 42
PSR Register Combinations ................................................................................. 48
Memory Map ....................................................................................................... 56
Memory Access Behavior ..................................................................................... 58
SRAM Memory Bit-Banding Regions .................................................................... 60
Peripheral Memory Bit-Banding Regions ............................................................... 60
Exception Types .................................................................................................. 66
Interrupts ............................................................................................................ 66
Exception Return Behavior ................................................................................... 71
Faults ................................................................................................................. 72
Fault Status and Fault Address Registers .............................................................. 73
Cortex-M3 Instruction Summary ........................................................................... 75
Core Peripheral Register Regions ......................................................................... 78
Peripherals Register Map ..................................................................................... 81
Interrupt Priority Levels ...................................................................................... 100
JTAG_SWD_SWO Signals (28SOIC) .................................................................. 122
JTAG_SWD_SWO Signals (48QFP) ................................................................... 123
JTAG Port Pins Reset State ............................................................................... 123
JTAG Instruction Register Commands ................................................................. 128
System Control & Clocks Signals (28SOIC) ......................................................... 132
System Control & Clocks Signals (48QFP) .......................................................... 132
Reset Sources ................................................................................................... 133
Clock Source Options ........................................................................................ 138
Possible System Clock Frequencies Using the SYSDIV Field ............................... 139
System Control Register Map ............................................................................. 142
PLL Mode Control .............................................................................................. 154
Flash Protection Policy Combinations ................................................................. 182
Flash Register Map ............................................................................................ 187
GPIO Pins With Non-Zero Reset Values .............................................................. 201
GPIO Pins and Alternate Functions (28SOIC) ...................................................... 201
GPIO Pins and Alternate Functions (48QFP) ....................................................... 201
GPIO Signals (28SOIC) ..................................................................................... 202
GPIO Signals (48QFP) ....................................................................................... 202
GPIO Pad Configuration Examples ..................................................................... 206
GPIO Interrupt Configuration Example ................................................................ 207
GPIO Register Map ........................................................................................... 208
Available CCP Pins ............................................................................................ 242
General-Purpose Timers Signals (28SOIC) ......................................................... 242
General-Purpose Timers Signals (48QFP) ........................................................... 243
16-Bit Timer With Prescaler Configurations ......................................................... 245
Timers Register Map .......................................................................................... 251
Watchdog Timer Register Map ............................................................................ 279
UART Signals (28SOIC) ..................................................................................... 302
10
July 14, 2014
Texas Instruments-Production Data