LM3S101 Datasheet, PDF (206/445 Pages) List of Unclassifed Manufacturers – Microcontroller

General-Purpose Input/Outputs (GPIOs)
conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a
GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller.
Interrupts are cleared by writing a 1 to the appropriate bit of the GPIO Interrupt Clear (GPIOICR)
register (see page 218).
When programming the following interrupt control registers, the interrupts should be masked (GPIOIM
set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can
generate a spurious interrupt if the corresponding bits are enabled.
7.3.3
Mode Control
The GPIO pins can be controlled by either hardware or software. When hardware control is enabled
via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 219), the pin state is
controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO
mode, where the GPIODATA register is used to read/write the corresponding pins.
7.3.4
Pad Control
The pad control registers allow for GPIO pad configuration by software based on the application
requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR,
GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. These registers control drive strength,
open-drain configuration, pull-up and pull-down resistors, slew-rate control and digital enable.
7.3.5
Identification
The identification registers configured at reset allow software to detect and identify the module as
a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as
well as the GPIOPCellID0-GPIOPCellID3 registers.
7.4 Initialization and Configuration
To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit
field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins (except for the five JTAG pins) default to general-purpose input mode
(GPIODIR=0 and GPIOAFSEL=0). Table 7-6 on page 206 shows all possible configurations of the
GPIO pads and the control register settings required to achieve them. Table 7-7 on page 207 shows
how a rising edge interrupt would be configured for pin 2 of a GPIO port.
Table 7-6. GPIO Pad Configuration Examples
Configuration
GPIO Register Bit Value^a
AFSEL DIR
ODR
DEN
Digital Input (GPIO)
0
0
0
1
Digital Output (GPIO)
0
1
0
1
Open Drain Output
0
1
1
1
(GPIO)
Digital Input (Timer
1
X
0
1
CCP)
Digital Output (Timer
1
X
0
1
PWM)
Digital Input/Output
1
X
0
1
(SSI)
PUR
?
?
X
?
?
?
PDR
?
?
X
?
?
?
DR2R
X
?
?
X
?
?
DR4R
X
?
?
X
?
?
DR8R
X
?
?
X
?
?
SLR
X
?
?
X
?
?
206
July 14, 2014
Texas Instruments-Production Data