LM3S101 Datasheet, PDF (14/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
Register 8: Flash Memory Protection Read Enable (FMPRE), offset 0x130 ......................................... 197
Register 9: Flash Memory Protection Program Enable (FMPPE), offset 0x134 .................................... 198
General-Purpose Input/Outputs (GPIOs) ................................................................................... 199
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 210
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 211
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 212
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 213
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 214
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 215
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 216
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 217
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 218
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 219
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 221
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 222
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 223
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 224
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 225
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 226
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 227
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 228
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 229
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 230
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 231
Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 232
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 233
Register 24: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 234
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 235
Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 236
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 237
Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 238
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 239
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 240
General-Purpose Timers ............................................................................................................. 241
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 253
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 254
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 256
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 258
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 261
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 263
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 264
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 265
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 267
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 268
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 269
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 270
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 271
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 272
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July 14, 2014
Texas Instruments-Production Data