LM3S101 Datasheet, PDF (8/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Table of Contents
List of Figures
Figure 1-1. Stellaris LM3S101 Microcontroller High-Level Block Diagram ................................. 30
Figure 1-2. LM3S101 Controller System-Level Block Diagram ................................................. 36
Figure 2-1. CPU Block Diagram ............................................................................................. 39
Figure 2-2. TPIU Block Diagram ............................................................................................ 40
Figure 2-3. Cortex-M3 Register Set ........................................................................................ 42
Figure 2-4. Bit-Band Mapping ................................................................................................ 61
Figure 2-5. Data Storage ....................................................................................................... 62
Figure 2-6. Vector Table ........................................................................................................ 68
Figure 2-7. Exception Stack Frame ........................................................................................ 70
Figure 4-1. JTAG Module Block Diagram .............................................................................. 122
Figure 4-2. Test Access Port State Machine ......................................................................... 126
Figure 4-3. IDCODE Register Format ................................................................................... 130
Figure 4-4. BYPASS Register Format ................................................................................... 131
Figure 4-5. Boundary Scan Register Format ......................................................................... 131
Figure 5-1. Basic RST Configuration .................................................................................... 134
Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 135
Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 135
Figure 5-4. Main Clock Tree ................................................................................................ 138
Figure 6-1. Flash Block Diagram .......................................................................................... 181
Figure 7-1. GPIO Module Block Diagram .............................................................................. 200
Figure 7-2. GPIO Port Block Diagram ................................................................................... 204
Figure 7-3. GPIODATA Write Example ................................................................................. 205
Figure 7-4. GPIODATA Read Example ................................................................................. 205
Figure 8-1. GPTM Module Block Diagram ............................................................................ 242
Figure 8-2. 16-Bit Input Edge Count Mode Example .............................................................. 246
Figure 8-3. 16-Bit Input Edge Time Mode Example ............................................................... 247
Figure 8-4. 16-Bit PWM Mode Example ................................................................................ 248
Figure 9-1. WDT Module Block Diagram .............................................................................. 278
Figure 10-1. UART Module Block Diagram ............................................................................. 302
Figure 10-2. UART Character Frame ..................................................................................... 303
Figure 11-1. SSI Module Block Diagram ................................................................................. 341
Figure 11-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 344
Figure 11-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 345
Figure 11-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 345
Figure 11-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 346
Figure 11-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 347
Figure 11-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 347
Figure 11-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 348
Figure 11-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 349
Figure 11-10. MICROWIRE Frame Format (Single Frame) ........................................................ 349
Figure 11-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 350
Figure 11-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 351
Figure 12-1. Analog Comparator Module Block Diagram ......................................................... 379
Figure 12-2. Structure of Comparator Unit .............................................................................. 381
Figure 12-3. Comparator Internal Reference Structure ............................................................ 382
Figure 13-1. 28-Pin SOIC Package Pin Diagram ..................................................................... 391
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July 14, 2014
Texas Instruments-Production Data