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LM3S101 Datasheet, PDF (138/445 Pages) List of Unclassifed Manufacturers – Microcontroller
System Control
The internal system clock (SysClk), is derived from any of the above sources plus two others: the
output of the main internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The
frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive).
Table 5-4 on page 138 shows how the various clock sources can be used in a system.
Table 5-4. Clock Source Options
Clock Source
Drive PLL?
Used as SysClk?
Internal Oscillator (12 MHz) Yes
BYPASS = 0, OSCSRC = 0x1 Yes
BYPASS = 1, OSCSRC = 0x1
Internal Oscillator divide by 4 (3 Yes
MHz)
BYPASS = 0, OSCSRC = 0x2 Yes
BYPASS = 1, OSCSRC = 0x2
Main Oscillator
Yes
BYPASS = 0, OSCSRC = 0x0 Yes
BYPASS = 1, OSCSRC = 0x0
5.2.4.2
Clock Configuration
Nearly all of the control for the clocks is provided by the Run-Mode Clock Configuration (RCC)
register. This register controls the following clock functionality:
■ Source of clocks in sleep and deep-sleep modes
■ System clock derived from PLL or other clock source
■ Enabling/disabling of oscillators and PLL
■ Clock divisors
■ Crystal input selection
Figure 5-4 on page 138 shows the logic for the main clock tree. The peripheral blocks are driven by
the system clock signal and can be individually enabled/disabled.
Figure 5-4. Main Clock Tree
OSC1
OSC2
Main
Osc
1-8 MHz
Internal
Osc
12 MHz
÷4
OSCSRCa
PLL
(200 MHz
output)
OENa
XTALa
PWRDNa
BYPASSa
USESYSDIVa
SYSDIVa
System Clock
a. These are bit fields within the Run-Mode Clock Configuration (RCC) register.
In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock
from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register
is configured). Table 5-5 shows how the SYSDIV encoding affects the system clock frequency,
depending on whether the PLL is used (BYPASS=0) or another clock source is used (BYPASS=1).
138
July 14, 2014
Texas Instruments-Production Data