LM3S101 Datasheet, PDF (42/445 Pages) List of Unclassifed Manufacturers – Microcontroller

The Cortex-M3 Processor
2.3.3
Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use
Processor Mode
Use
Thread
Applications
Handler
Exception handlers
a. See CONTROL (page 55).
Privilege Level
Privileged or unprivileged ^a
Always privileged
Stack Used
Main stack or process stack ^a
Main stack
Register Map
Figure 2-3 on page 42 shows the Cortex-M3 register set. Table 2-2 on page 42 lists the Core
registers. The core registers are not memory mapped and are accessed by register name, so the
base address is n/a (not applicable) and there is no offset.
Figure 2-3. Cortex-M3 Register Set
Low registers
High registers
Stack Pointer
Link Register
Program Counter
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
SP (R13)
LR (R14)
PC (R15)
PSR
PRIMASK
FAULTMASK
BASEPRI
CONTROL
General-purpose registers
PSP^‡
MSP^‡
Program status register
Exception mask registers
CONTROL register
‡_{Banked version of SP}
Special registers
Table 2-2. Processor Register Map
Offset Name
Type
-
R0
R/W
-
R1
R/W
-
R2
R/W
-
R3
R/W
Reset
-
-
-
-
Description
Cortex General-Purpose Register 0
Cortex General-Purpose Register 1
Cortex General-Purpose Register 2
Cortex General-Purpose Register 3
See
page
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July 14, 2014
Texas Instruments-Production Data