LM3S101 Datasheet, PDF (139/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S101 Microcontroller
5.2.4.3
5.2.4.4
The divisor is equivalent to the SYSDIV encoding plus 1. For a list of possible clock sources, see
Table 5-4 on page 138.
Table 5-5. Possible System Clock Frequencies Using the SYSDIV Field
SYSDIV
0x0
Divisor
/1
Frequency
(BYPASS=0)
reserved
Frequency (BYPASS=1)
Clock source frequency/2
StellarisWare Parameter^a
SYSCTL_SYSDIV_1^b
0x1
/2 reserved
Clock source frequency/2
SYSCTL_SYSDIV_2
0x2
/3 reserved
Clock source frequency/3
SYSCTL_SYSDIV_3
0x3
/4 reserved
Clock source frequency/4
SYSCTL_SYSDIV_4
0x4
/5 reserved
Clock source frequency/5
SYSCTL_SYSDIV_5
0x5
/6 reserved
Clock source frequency/6
SYSCTL_SYSDIV_6
0x6
/7 reserved
Clock source frequency/7
SYSCTL_SYSDIV_7
0x7
/8 reserved
Clock source frequency/8
SYSCTL_SYSDIV_8
0x8
/9 reserved
Clock source frequency/9
SYSCTL_SYSDIV_9
0x9
/10 20 MHz
Clock source frequency/10
SYSCTL_SYSDIV_10
0xA
/11 18.18 MHz
Clock source frequency/11
SYSCTL_SYSDIV_11
0xB
/12 16.67 MHz
Clock source frequency/12
SYSCTL_SYSDIV_12
0xC
/13 15.38 MHz
Clock source frequency/13
SYSCTL_SYSDIV_13
0xD
/14 14.29 MHz
Clock source frequency/14
SYSCTL_SYSDIV_14
0xE
/15 13.33 MHz
Clock source frequency/15
SYSCTL_SYSDIV_15
0xF
/16 12.5 MHz (default) Clock source frequency/16
SYSCTL_SYSDIV_16
a. This parameter is used in functions such as SysCtlClockSet() in the Stellaris Peripheral Driver Library.
b. SYSCTL_SYSDIV_1 does not set the USESYSDIV bit. As a result, using this parameter without enabling the PLL results
in the system clock having the same frequency as the clock source.
Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals. If the main oscillator is used by
the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise,
the range of supported crystals is 1 to 8.192 MHz.
The XTAL bit in the RCC register (see page 152) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software configures the main PLL input reference clock source, specifies the output divisor
to set the system clock frequency, and enables the main PLL to drive the output.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the XTAL to PLL Translation
(PLLCFG) register (see page 155). The internal translation provides a translation within ± 1% of the
targeted PLL VCO frequency.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 152)
describes the available crystal choices and default programming of the PLLCFG register. Any time
the XTAL field changes, the new settings are translated and the internal PLL settings are updated.
July 14, 2014
139
Texas Instruments-Production Data