LM3S101 Datasheet, PDF (40/445 Pages) List of Unclassifed Manufacturers – Microcontroller

The Cortex-M3 Processor
2.2.3
If a patch is required, the application programs the FPB to remap a number of addresses. When
those addresses are accessed, the accesses are redirected to a remap table specified in the FPB
configuration.
For more information on the Cortex-M3 debug capabilities, see theARM® Debug Interface V5
Architecture Specification.
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer, as shown in Figure 2-2 on page 40.
Figure 2-2. TPIU Block Diagram
Debug
ATB
Slave
Port
ATB
Interface
Asynchronous FIFO
Trace Out
(serializer)
Serial Wire
Trace Port
(SWO)
APB
Slave
Port
APB
Interface
2.2.4
Cortex-M3 System Component Details
The Cortex-M3 includes the following system components:
■ SysTick
A 24-bit count-down timer that can be used as a Real-Time Operating System (RTOS) tick timer
or as a simple counter (see “System Timer (SysTick)” on page 78).
■ Nested Vectored Interrupt Controller (NVIC)
An embedded interrupt controller that supports low latency interrupt processing (see “Nested
Vectored Interrupt Controller (NVIC)” on page 79).
■ System Control Block (SCB)
The programming model interface to the processor. The SCB provides system implementation
information and system control, including configuration, control, and reporting of system exceptions
(see “System Control Block (SCB)” on page 81).
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July 14, 2014
Texas Instruments-Production Data