LM3S101 Datasheet, PDF (13/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S101 Microcontroller
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 104
System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 106
System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 107
System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 108
System Handler Control and State (SYSHNDCTRL), offset 0xD24 .................................... 109
Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 113
Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 118
Memory Management Fault Address (MMADDR), offset 0xD34 ........................................ 119
Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 120
System Control ............................................................................................................................ 132
Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 144
Register 2: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 .................................. 146
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................. 147
Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 148
Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 149
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 150
Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 151
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 152
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 ............................................................. 155
Register 10: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 ........................................ 156
Register 11: Clock Verification Clear (CLKVCLR), offset 0x150 ............................................................ 157
Register 12: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ................................. 158
Register 13: Device Identification 1 (DID1), offset 0x004 ..................................................................... 159
Register 14: Device Capabilities 0 (DC0), offset 0x008 ........................................................................ 161
Register 15: Device Capabilities 1 (DC1), offset 0x010 ........................................................................ 162
Register 16: Device Capabilities 2 (DC2), offset 0x014 ........................................................................ 163
Register 17: Device Capabilities 3 (DC3), offset 0x018 ........................................................................ 164
Register 18: Device Capabilities 4 (DC4), offset 0x01C ....................................................................... 165
Register 19: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 ................................... 166
Register 20: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 ................................. 167
Register 21: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 168
Register 22: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 169
Register 23: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 171
Register 24: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 173
Register 25: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 175
Register 26: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 176
Register 27: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 177
Register 28: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 178
Register 29: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 179
Register 30: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 180
Internal Memory ........................................................................................................................... 181
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 188
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 189
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 190
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 192
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 193
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 194
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 196
July 14, 2014
13
Texas Instruments-Production Data