LM3S101 Datasheet, PDF (15/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S101 Microcontroller
Register 15:
Register 16:
Register 17:
Register 18:
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 273
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 274
GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 275
GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 276
Watchdog Timer ........................................................................................................................... 277
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 281
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 282
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 283
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 284
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 285
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 286
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 287
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 288
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 289
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 290
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 291
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 292
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 293
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 294
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 295
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 296
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 297
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 298
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 299
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 300
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 301
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 309
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 311
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 313
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 315
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 316
Register 6: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 317
Register 7: UART Control (UARTCTL), offset 0x030 ......................................................................... 319
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 321
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 323
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 325
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 326
Register 12: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 327
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 329
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 330
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 331
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 332
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 333
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 334
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 335
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 336
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 337
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 338
July 14, 2014
15
Texas Instruments-Production Data