LM3S101 Datasheet, PDF (75/445 Pages) List of Unclassifed Manufacturers – Microcontroller

Stellaris^® LM3S101 Microcontroller
■ Braces, {}, enclose optional operands
■ The Operands column is not exhaustive
■ Op2 is a flexible second operand that can be either a register or a constant
■ Most instructions can use an optional condition code suffix
For more information on the instructions and operands, see the instruction descriptions in
the Cortex™-M3/M4 Instruction Set Technical User's Manual.
Table 2-13. Cortex-M3 Instruction Summary
Mnemonic
ADC, ADCS
ADD, ADDS
ADD, ADDW
ADR
AND, ANDS
ASR, ASRS
B
BFC
BFI
BIC, BICS
BKPT
BL
BLX
BX
CBNZ
CBZ
CLREX
CLZ
CMN
CMP
CPSID
Operands
{Rd,} Rn, Op2
{Rd,} Rn, Op2
{Rd,} Rn , #imm12
Rd, label
{Rd,} Rn, Op2
Rd, Rm, <Rs|#n>
label
Rd, #lsb, #width
Rd, Rn, #lsb, #width
{Rd,} Rn, Op2
#imm
label
Rm
Rm
Rn, label
Rn, label
-
Rd, Rm
Rn, Op2
Rn, Op2
i
CPSIE
i
DMB
DSB
EOR, EORS
ISB
IT
LDM
LDMDB, LDMEA
-
-
{Rd,} Rn, Op2
-
-
Rn{!}, reglist
Rn{!}, reglist
LDMFD, LDMIA
LDR
LDRB, LDRBT
LDRD
Rn{!}, reglist
Rt, [Rn, #offset]
Rt, [Rn, #offset]
Rt, Rt2, [Rn, #offset]
Brief Description
Flags
Add with carry
N,Z,C,V
Add
N,Z,C,V
Add
N,Z,C,V
Load PC-relative address
-
Logical AND
N,Z,C
Arithmetic shift right
N,Z,C
Branch
-
Bit field clear
-
Bit field insert
-
Bit clear
N,Z,C
Breakpoint
-
Branch with link
-
Branch indirect with link
-
Branch indirect
-
Compare and branch if non-zero
-
Compare and branch if zero
-
Clear exclusive
-
Count leading zeros
-
Compare negative
N,Z,C,V
Compare
N,Z,C,V
Change processor state, disable
-
interrupts
Change processor state, enable
-
interrupts
Data memory barrier
-
Data synchronization barrier
-
Exclusive OR
N,Z,C
Instruction synchronization barrier
-
If-Then condition block
-
Load multiple registers, increment after -
Load multiple registers, decrement
-
before
Load multiple registers, increment after -
Load register with word
-
Load register with byte
-
Load register with two bytes
-
July 14, 2014
75
Texas Instruments-Production Data