TLK111_14 Datasheet, PDF (77/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
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SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
Table 8-38. TX_CLK Phase Shift Register (TXCPSR), address 0x0042 (continued)
BIT NAME
DEFAULT
4 Phase Shift 0,RW,SC
Enable
3:0 Phase Shift 0000,RW
Value
FUNCTION
TX Clock Phase Shift Enable:
1 = Perform Phase Shift to the TX_CLK according to the value written to Phase Shift Value in bits
[4:0].
0 = No change in TX Clock phase
TX Clock Phase Shift Value:
The value of this register represents the current phase shift between Reference clock at XI and MII
Transmit Clock at TX_CLK. Any different value that will be written to these bits will shift TX_CLK by 4
times the difference (in nSec).
For example, if the value of this register is 0x2, Writing 0x9 to this register shifts TX_CLK by 28nS (4
times 7).However, since the maximum difference between XI and TX_CLK could be 40nSec (value of
10) in case of writing value bigger than 10, the updated value is the written value modulo 10.
8.9 Power Back Off Control Register (PWRBOCR)
Table 8-39. Power Back Off Control Register (PWRBOCR), address 0x00AE
BIT NAME
DEFAULT
15 RESERVED 1, RO
14 RESERVED 0, RO
13:9 RESERVED 00 000, RO
8:6 Power Back 0, RW
Off
5:0 RESERVED 10 0000, RO
FUNCTION
RESERVED
RESERVED
RESERVED
Power Back Off Level: See Application Note SLLA328
000 = Normal Operation
001 = Level 1 (up to 5m cable between TLK link partners)
010 = Level 2 (up to 80m cable between TLK link partners)
011 = Level 3 (up to 100m cable between TLK link partners)
Others = Reserved
RESERVED
8.10 Voltage Regulator Control Register (VRCR)
This register gives the host processor the ability to power down the voltage-regulator block of the PHY via
register access. This power-down operation is available in systems operating with an external power
supply.
Table 8-40. Voltage Regulator Control Register (VRCR), address 0x00D0
BIT NAME
DEFAULT
FUNCTION
15 VRPD
0, RW, SC
Voltage Regulator Power Down:
1 = Power Down. Allow the system to power down the voltage regulator block of the PHY
using register access.
0 = Normal Operation. Voltage Regulator is powered and outputs voltage on the PFBOUT
pin.
14:4 RESERVED 000 0000 0000, RW RESERVED: Must be written as 0.
3:0 VR Control 0000, RW
Voltage Regulator Control This value should be ignored on read. To write to this register,
perform a read followed by a write with the desired value.
8.11 Fiber Mode Control Register 2 (FIBCR2)
Table 8-41. Fiber Mode Control Register 2 (FIBCR2), address 0x00FD
BIT NAME
DEFAULT
15 FX FEF faulting RO,LH
status
14 FX PECL
RO,LH
Signaling status
13 FX SD Status RO,LL
12:10 RESERVED
011, RO
FUNCTION
Asserted when the FEF (Far-End Fault) detection mechanism detec FEF signaling from
the far-end peer
Asserted if the FX reciever detects violation of the PECL signaling from the optic
transceiver (such as glitches or invalid pulse width)
Indicates the Status of SD_IN signal in the fiber RX path. If SD_IN is deasserted, it will be
latched low. Upon read, the value of the bit will be updated with current value.
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