TLK111_14 Datasheet, PDF (76/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
www.ti.com
Table 8-35. IEEE1588 Precision Timing Pin Select (PTPPSEL), address 0x003E (continued)
BIT
BIT NAME
6:4 cfg_1588_TX_pin_sel
3 RESERVED
2:0 cfg_1588_RX_pin_sel
DEFAULT
0, RW
0, RO
0, RW
DESCRIPTION
IEEE 1588 TX Pin Select: Assigns transmit SFD
pulse indication to pin selected by value in column at
right.
RESERVED: Writes ignored, read as 0.
IEEE 1588 RX Pin Select: Assigns receive SFD
pulse indication to pin selected by value in column at
right.
001 - LED_ACT Pin
010 - LED_SPEED Pin
011 - LED_LINK Pin
100- CRS Pin
101 - COL Pin
110 - PWDNN/INT Pin
111 - No pulse output
8.6 IEEE1588 Precision Timing Configuration (PTPCFG)
This register allows programming the length of the generated packets in bytes for the BIST mechanism.
Table 8-36. IEEE1588 Precision Timing Configuration (PTPCFG), address 0x003F
BIT
BIT NAME
DEFAULT
DESCRIPTION
15:13 cfg_1588_TX_set_phase <101>, RW PTP Transmit Timing: Set 1588 indication for TX path (8ns step)
12:10 cfg_1588_RX_set_phase <101>, RW PTP Receive TIming: Set 1588 indication for RX path (8ns step)
9:8 cfg_TX_ERR_sel
0, (TRIM)
Configure TX ERR Input Pin:
00 - No TX ERR
01 - Use LED ACT as TX_ERR
10 - Use PWRDN as TX_ERR
11 - USe COL as TX_ERR
7:0 RESERVED
<0100 0100>, RESERVED
RW
8.7 Fiber Mode Control Register (FIBCR)
Table 8-37. Fiber Mode Control Register (FIBCR), address 0x0040
BIT
15:14
13
12:7
6
NAME
DEFAULT
RESERVED
01, RW
BIST Force Link 1, RW
Indication
RESERVED
0 0000 1, RW
FEF Gen
Disable
0, RW,SC
5
FEF Det
Disable
0, RW,SC
4:0 RESERVED
1 1101, RO
FUNCTION
Force Emulation of Link indication from PHY (regardless to actual link status), Part of BIST
options to check MAC SW
FEF Gen Disable:
1 = Disable the ability to generate FEF sequence in the TX path
0 = Enable FEF sequence generation
FEF Det Disable:
1 = Disable the ability to detect FEF sequence in the RX path
0 = Enable FEF sequence detection
Writes ignored, read as 0
8.8 TX_CLK Phase Shift Register (TXCPSR)
This register allows programming the phase of the MII transmit clock (TX_CLK pin). The TX_CLK has a
fixed phase to the XI pin. However the default phase, while fixed, may not be ideal for all systems,
therefore this register may be used by the system to align the reference clock (XI pin) to the TX_CLK. The
phase shift value is in 4ns units. The phase shift value should be between 0 and 10 (0ns to 40ns). If value
greater than 10 is written, the update value will be the written value modulo 10.
Table 8-38. TX_CLK Phase Shift Register (TXCPSR), address 0x0042
BIT NAME
DEFAULT
15:5 RESERVED 0000 0000
000, RO
FUNCTION
RESERVED: Writes ignored, read as 0
76
Register Block
Submit Documentation Feedback
Product Folder Links: TLK111
Copyright © 2013–2014, Texas Instruments Incorporated