TLK111_14 Datasheet, PDF (59/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
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SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
8.1.10 Software Strap Control register 1 (SWSCR1)
This register contains the configuration bits used as strapping options or virtual strapping pins during HW
RESET. These configuration values are programmed by the system processor after HW_RESET/POR,
and then the “Config Done” - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration. An
internal reset pulse is generated and the SW Strap bit values are latched into internal registers.
Table 8-13. SW Strap Control register 1 (SWSCR1), address 0x0009
BIT BIT NAME
15 SW Strap
Config Done
14 Auto MDI-X
Enable
13 Auto-
Negotiation
Enable
12:11 AN[1:0]
10 LED_CFG
DEFAULT
0, RW
1, SWSC, RW
1, SWSC, RW
1, SWSC, RW
1, SWSC, RW
DESCRIPTION
Software Strap Configuration Done:
1 = SW Strap configuration is complete, and the PHY can continue and complete its
internal reset sequence.
0 = SW strap configuration process is not complete
Auto MDI/MDIX Enable:
1 = Enable automatic crossover
0 = Disable automatic crossover
This bit determines whether Automatic MDI/MDIX crossover is enabled or not. If Strapping
Pin configuration is override, the value of this register is latched at RESET to bit 15 of
PHYCR register (0x0019) and defines its value.
Auto-Negotiation Enable:
1 = Auto-Negotiation Enabled
0 = Auto-Negotiation Disabled – Force mode is active
This bit determines whether Auto-negotiation is enabled
Auto-Negotiation Mode [1:0]:
ANEN
AN_1
AN_0
Forced Mode
0
0
0
10Base-T, Half-Duplex
0
0
1
10Base-T, Full-Duplex
0
1
0
100Base-TX, Half-Duplex
0
1
1
100Base-TX, Full-Duplex
ANEN
AN_1
AN_0
Advertised Mode
1
0
0
10Base-T, Half or Full-Duplex
1
0
1
100Base-TX, Half or Full-Duplex
1
1
0
10Base-T,Half-Duplex
100Base-TX, Half-Duplex
1
1
1
10Base-T,Half or Full-Duplex
100Base-TX, Half or Full-Duplex
If the Strapping Pin configuration is override, the decoded value of these 3 register bits
are latched at RESET to the appropriate bits of BMCR (0x0000) and ANAR (0x0004) and
define their values.
LED Configuration:
1 = Select LED configuration Mode 1
0 = Select LED configuration Mode 2 or 3 according to LEDCR register (0x0018) bit 5
and 6.
If the Strapping Pin configuration is override, the value of this register is latched at RESET
to bit 5 of the PHYCR register (0x0019) and defines its value.
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