TLK111_14 Datasheet, PDF (5/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
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SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
2.2 Serial Management Interface (SMI)
PIN
NAME NO.
MDC
31
MDIO
30
TYPE
DESCRIPTION
MANAGEMENT DATA CLOCK: Clock signal for the management data input/output (MDIO) interface. The
I maximum MDC rate is 25MHz; there is no minimum MDC rate. MDC is not required to be synchronous to the
TX_CLK or the RX_CLK.
I/O
MANAGEMENT DATA I/O: Bidirectional command / data signal synchronized to MDC. Either the local
controller or the TLK111 may drive the MDIO signal. This pin requires a pull-up resistor with value 2.2kΩ.
2.3 MAC Data Interface
PIN
NAME
TYPE
NO.
DESCRIPTION
TX_CLK
MII TRANSMIT CLOCK: MII Transmit Clock provides the 25MHz or 2.5MHz reference clock
depending on the speed. Note that in MII mode, this clock has constant phase referenced to
1
O, PD REF_CLK. Applications requiring such constant phase may use this feature.
Unused in RMII mode. In RMII, X1 reference clock is used as the clock for both transmit and
receive.
TX_EN
TRANSMIT ENABLE: TX_EN is presented on the rising edge of the TX_CLK . TX_EN
2
I, PD indicates the presence of valid data inputs on TXD[3:0] in MII mode, and on TXD [1:0] in the
RMII mode. TX_EN is an active high signal.
TXD_0
TXD_1
TXD_2
TXD_3
3
4
5
6
I, PD
TRANSMIT DATA: In MII mode, the transmit data nibble received from the MAC is
synchronous to the rising edge of the TX_CLK signal. In RMII mode, TXD [1:0] received from
the MAC is synchronous to the 50MHz reference clock on XI.
RX_CLK
38
O
RECEIVE CLOCK: In MII mode it is the receive clock that provides either a 25MHz or 2.5MHz
reference clock, depending on the speed, that is derived from the received data stream.
RX_DV / MII_MODE
39
S, O, PD
RECEIVE DATA VALID: This pin indicates valid data is present on the RXD [3:0] for MII mode
or on RXD [1:0] for RMII mode, independently from Carrier Sense.
RECEIVE ERROR: This pin indicates that an error symbol has been detected within a received
RX_ER / AMDIX_EN
41
S, O, PU
packet in both MII and RMII mode. In MII mode, RX_ER is asserted high synchronously to
RX_CLK and in RMII mode, synchronously to XI (50MHz). This pin is not required to be used
by the MAC, in either MII or RMII, because the PHY is corrupting data on a receive error.
RXD_0 / PHYAD1
RXD_1 / PHYAD2
RXD_2 / PHYAD3
RXD_3 / PHYAD4
RECEIVE DATA: Symbols received on the cable are decoded and presented on these pins
synchronous to RX_CLK. They contain valid data when RX_DV is asserted. A nibble RXD [3:0]
43
is received in the MII mode and 2-bits RXD[1:0] is received in the RMII Mode.
44
45
S, O, PD _{PHY address pins PHYAD[4:1] are multiplexed with RXD [3:0], and are pulled down. PHYAD0}
46
(LSB of the address) is multiplexed with COL on pin 42, and is pulled up.
If no external pullup/pulldown is present, the default address is 0x01.
CRS / LED_CFG
CARRIER SENSE: In MII mode this pin is asserted high when the receive medium is non-idle.
40 S, O, PU
CARRIER SENSE/RECEIVE DATA VALID: In RMII mode, this pin combines the RMII Carrier
and Receive Data Valid indications.
COL / PHYAD0
COLLISION DETECT: For MII mode in Full Duplex Mode this pin is always low. In 10Base-
42 S, O, PU _{T/100Base-TX half-duplex modes, this pin is asserted HIGH only when both transmit and}
receive media are non-idle. This pin is not used in RMII mode.
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