TLK111_14 Datasheet, PDF (62/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
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8.1.11 Software Strap Control register 2 (SWSCR2)
This register contains the configuration bits used as strapping options or virtual strapping pins during HW
RESET. These configuration values are programmed by the system processor after HW_RESET/POR,
and then the “Config Done” - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration. An
internal reset pulse is generated and the SW Strap bit values are latched into internal registers.
Table 8-14. SW Strap Control register 2 (SWSCR2), address 0x000A
BIT BIT NAME
15 100BT Force
Far-End Link
drop
14 Fiber Mode
Control
13:7 RESERVED
6 Fast Link-Up in
Parallel Detect
5 Extended FD
Ability
DEFAULT
0, RW
0, RW
2, SWS, RW
0, SWS, RW
0, SWS, RW
DESCRIPTION
100BT Force Far-End Link drop: Writing a 1 asserts the 100BT Force Far-End link drop
mode. In this mode (only valid in force 100BT), the PHY disables the TX upon link drop to
allow the far-end peer to drop its link as well, thus allowing both link partners be aware of
the system link failure. This mode exceeds the standard definition of force 100BT.
Fiber Mode Control:
1 = Enable Fiber Mode
0 = Disable Fiber Mode
RESERVED
Fast Link-Up in Parallel Detect Mode:
1 = Enable Fast Link-Up time During Parallel Detection
0 = Normal Parallel Detection link establishment
In Fast Auto MDI-X and in Robust Auto MDI-X modes (bits 6 and 5 in register SWSCR1),
this bit is automatically set.
Extended Full-Duplex Ability:
1 = Force Full-Duplex while working with link partner in forced 100B-TX. When the
PHY is set to Auto-Negotiation or Force 100B-TX and the link partner is operated
in Force 100B-TX, the link is always Full Duplex
0 = Disable Extended Full Duplex Ability. Decision to work in Full Duplex or Half
Duplex mode follows IEEE specification.
4 Enhanced LED
Link
3 Isolate MII in
100BT HD
2 RXERR During
IDLE
1 Odd-Nibble
Detection
Disable
0 RMII Receive
Clock
0, SWS, RW
0, SWS, RW
1, SWS, RW
0, SWS, RW
0, SWS, RW
Enhanced LED Link Functionality:
1 = LED Link is ON only when link is established in 100B-TX Full Duplex mode.
0 = LED Link is ON when link is established.
Isolate MII outputs when FD Link @ 100BT is not achievable:
1 = When HD link established in 100B-TX MII outputs are isolated
0 = Normal MII outputs operation
Detection of Receive Symbol Error During IDLE State:
1 = Enable detection of Receive symbol error during IDLE state
0 = Disable detection of Receive symbol error during IDLE state.
Detection of Transmit Error:
1 = Disable detection of transmit error in odd-nibble boundary
0 = Enable detection of de-assertion of TX_EN on an odd-nibble boundary. In this case
TX_EN is extended by one additional TX_CLK cycle and behaves as if TX_ER
were asserted during that additional cycle.
RMII Receive Clock:
1 = RMII Data (RXD [1:0]) is sampled and referenced to RX_CLK
0 = RMII Data (RXD [1:0]) is sampled and referenced to XI
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Register Block
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