TLK111_14 Datasheet, PDF (24/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
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4.3 Serial Management Interface
The Serial Management Interface (SMI), provides access to the TLK111 internal register space for status
information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The implemented
register set consists of all the registers required by the IEEE802.3-2002, plus several others to provide
additional visibility and controllability of the TLK111 device.
The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock
is sourced by the external management entity, also called Station (STA), and can run at a maximum clock
rate of 25MHz. MDC is not expected to be continuous, and can be turned off by the external management
entity when the bus is idle.
The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is
latched on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (2.2kΩ) which,
during IDLE and turnaround, pulls MDIO high.
Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used.
During power-up reset, the TLK111 latches the PHYAD[4:0] configuration pins (Pin 42 to Pin 46) to
determine its address.
The management entity must not start an SMI transaction in the first cycle after power-up reset. To
maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is de-
asserted.
In normal MDIO transactions, the register address is taken directly from the management-frame reg_addr
field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE802.3 and vendor
specific). The data field is used for both reading and writing. The Start code is indicated by a <01> pattern.
This pattern makes sure that the MDIO line transitions from the default idle line state. Turnaround is
defined as an idle bit time inserted between the Register Address field and the Data field. To avoid
contention during a read transaction, no device may actively drive the MDIO signal during the first bit of
Turnaround. The addressed TLK111 drives the MDIO with a zero for the second bit of turnaround and
follows this with the required data. Figure 4-3 shows the timing relationship between MDC and the MDIO
as driven/received by the Station (STA) and the TLK111 (PHY) for a typical register read access.
For write transactions, the station-management entity writes data to the addressed TLK111, thus
eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity
by inserting <10>. Figure 4-4 shows the timing relationship for a typical MII register write access. The
frame structure and general read/write transactions are shown in Table 4-2, Figure 4-3, and Figure 4-4.
MII Management Serial Protocol
Read Operation
Write Operation
Table 4-2. Typical MDIO Frame Format
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
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