TLK111_14 Datasheet, PDF (3/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
www.ti.com
SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
1 Introduction .............................................. 1
1.1 Features ............................................. 1
1.2 Applications .......................................... 1
1.3 Device Overview ..................................... 1
2 Pin Descriptions ......................................... 4
2.1 Pin Layout ........................................... 4
2.2 Serial Management Interface (SMI) ................. 5
2.3 MAC Data Interface .................................. 5
2.4 10Mbs and 100Mbs PMD Interface .................. 6
2.5 Clock Interface ....................................... 6
2.6 LED Interface ........................................ 6
2.7 JTAG Interface ....................................... 6
2.8 Reset and Power Down ............................. 7
2.9 Power and Bias Connections ........................ 7
2.10 Fiber Interface ....................................... 7
3 Hardware Configuration ............................... 8
3.1 Bootstrap Configuration .............................. 8
3.2 Power Supply Configuration ........................ 10
3.3 IO Pins Hi-Z State During Reset ................... 12
3.4 Auto-Negotiation .................................... 12
3.5 Auto-MDIX .......................................... 13
3.6 PHY Address ....................................... 13
3.7 MII Isolate Mode .................................... 14
3.8 Software Strapping Mode .......................... 14
3.9 LED Interface ....................................... 16
3.10 Multi-Configurable LED (MLED) .................... 17
3.11 Loopback Functionality ............................. 17
3.12 BIST ................................................ 19
3.13 Cable Diagnostics .................................. 20
4 Interfaces ................................................ 21
4.1 Media Independent Interface (MII) ................. 21
4.2 Reduced Media Independent Interface (RMII) ..... 22
4.3 Serial Management Interface ....................... 24
5 Architecture ............................................. 28
5.1 100Base-TX Transmit Path ......................... 28
5.2 100Base-TX Receive Path ......................... 31
5.3 10Base-T Receive Path ............................ 33
5.4 Auto Negotiation .................................... 34
5.5 Link Down Functionality ............................ 36
5.6 100BaseX Fiber Mode .............................. 37
5.7 IEEE 1588 Precision Timing Protocol Support ..... 37
6 Reset and Power Down Operation ................. 39
6.1 Hardware Reset .................................... 39
6.2 Software Reset ..................................... 39
6.3 Power Down/Interrupt .............................. 39
6.4 Power Save Modes ................................. 40
7 Design Guidelines ..................................... 41
7.1 TPI Network Circuit ................................. 41
7.2 Clock In (XI) Requirements ......................... 41
7.3 Thermal Vias Recommendation .................... 43
7.4 Fiber Networking Circuit ............................ 43
8 Register Block ......................................... 44
8.1 Register Definition .................................. 50
8.2 Cable Diagnostic Control Register (CDCR) ........ 74
8.3 PHY Reset Control Register (PHYRCR) ........... 75
8.4 Multi LED Control register (MLEDCR) ............. 75
8.5 IEEE1588 Precision Timing Pin Select (PTPPSEL)
...................................................... 75
8.6 IEEE1588 Precision Timing Configuration
(PTPCFG) .......................................... 76
8.7 Fiber Mode Control Register (FIBCR) .............. 76
8.8 TX_CLK Phase Shift Register (TXCPSR) .......... 76
8.9 Power Back Off Control Register (PWRBOCR) .... 77
8.10 Voltage Regulator Control Register (VRCR) ....... 77
8.11 Fiber Mode Control Register 2 (FIBCR2) .......... 77
8.12 Fiber Mode Control Register 3 (FIBCR3) .......... 78
8.13 Cable Diagnostic Configuration/Result Registers .. 78
9 Electrical Specifications ............................. 84
9.1 ABSOLUTE MAXIMUM RATINGS ................. 84
9.2 RECOMMENDED OPERATING CONDITIONS .... 84
9.3 48-Pin Industrial Device Thermal Characteristics .. 84
9.4 48-Pin Extended Temperature (125°C) Device
Thermal Characteristics ............................ 85
9.5 DC CHARACTERISTICS, VDD_IO ................ 85
9.6 DC CHARACTERISTICS, SD_IN .................. 85
9.7 DC CHARACTERISTICS ........................... 85
9.8 Power Supply Characteristics ...................... 87
9.9 AC Specifications ................................... 88
Revision History, Revision A ........................... 103
Revision History, Revision B ........................... 103
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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