TLK111_14 Datasheet, PDF (7/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
www.ti.com
SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
PIN
NAME
JTAG_TMS
JTAG_TRST
TYPE
NO.
DESCRIPTION
10
I, PU JTAG Test Mode Select: This pin has a weak internal pullup.
11
I, PU JTAG Reset: This pin is an active-low asynchronous test reset with a weak internal pullup.
2.8 Reset and Power Down
PIN
NAME
RESET
INT / PWDN
TYPE
NO.
DESCRIPTION
This pin is an active-low reset input that initializes or re-initializes all the internal registers of the
29
I, PU TLK111. Asserting this pin low for at least 1µs will force a reset process to occur. All jumper
options are reinitialized as well.
Register access is required for this pin to be configured either as power down or as an interrupt.
The default function of this pin is power down.
When this pin is configured for a power down function, an active low signal on this pin places the
7 IO, OD, PU device in power down mode.
When this pin is configured as an interrupt pin, then this pin is asserted low when an interrupt
condition occurs. The pin has an open-drain output with a weak internal pull-up. Some
applications may require an external pull-up resistor.
2.9 Power and Bias Connections
PIN
NAME
RBIAS
PFBOUT
PFBIN1
PFBIN2
VDD_IO
IOGND
DGND
AVDD33
AGND
RESERVED
NO.
24
23
18
37
32, 48
35, 47
36
22
15, 19
20
TYPE
DESCRIPTION
I Bias Resistor Connection: Use a 4.87kΩ 1% resistor connected from RBIAS to GND.
O Power Feedback Output: Place 10µf and 0.1μF capacitors (ceramic preferred) close to PFBOUT.
In single-supply operation, connect this pin to PFBIN1 and PFBIN2 (pin 18 and pin 37). See Figure 3-1
for proper placement.
In multiple supply operation, this pin is not used.
Power Feedback Input: These pins are fed with power from PFBOUT (pin 23) in single supply
operation.
I _{In multiple supply operation, connect a 1.55V external power supply to these pins. Connect a small}
capacitor of 0.1µF close to each pin. To power down the internal linear regulator, write to register
0x00d0.
P I/O 3.3V, 2.5V, or 1.8V Supply - For details, see Section 3.2.3
P I/O ground
P Digital ground
P Analog 3.3V power supply
P Analog ground
I/O RESERVED: This pin must be pulled-up through 2.2kΩ resistor to AVDD33 supply.
2.10 Fiber Interface
(See Table 3-3 for LED Mode Selection)
PIN
NAME
SD_IN
(LED_SPEED) /
AN_1
TYPE
NO.
DESCRIPTION
When Fiber mode is enabled, this Pin becomes an input driven by the SD_IN signal from the optic
transceiver. This pins indicates to the FX state machines whether or not the signal was detected on
27 S, I, PU the optic transceiver. The TLK111 also supports other modes for FX mode that do not require this
input (For further information see FIBCR2 (0x00FD) and FIBCR3 ( 0x0102) regsiters). This pin
supports Threshold levels of PECL signaling (3.3VDDIO levels; see Section 9.6).
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Pin Descriptions
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