TLK111_14 Datasheet, PDF (12/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
3.3 IO Pins Hi-Z State During Reset
The following IO or output pins are in hi-Z state when RESET is active (Low).
Pin Name
TXD_3
TX_EN
INT/PWDN
LED_ACT
LED_SPEED
LED_LINK
MDIO
RX_DV
CRS
Type
IO
IO
IO
IO
IO
IO
IO
IO
IO
Internal
PU/PD
PD
PD
PU
PU
PU
PU
PD
PU
Pin Name
RX_ER
COL
RXD_0
RXD_1
RXD_2
RXD_3
TX_CLK
CLK25MHz_OUT
RX_CLK
Type
IO
IO
IO
IO
IO
IO
O
O
O
Internal
PU/PD
PU
PU
PD
PD
PD
PD
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3.4 Auto-Negotiation
The TLK111 device auto-negotiates to operate in 10Base-T or 100Base-TX. With Auto-Negotiation
enabled, the TLK111 negotiates with the link partner to determine the speed and duplex mode. If the link
partner cannot Auto-Negotiate, the TLK111 device enters parallel-detect mode to determine the speed of
the link partner. Parallel-detect mode uses fixed half-duplex mode.
The TLK111 supports four different Ethernet protocols (10Mbs Half-Duplex, 10Mbs Full-Duplex, 100Mbs
Half-Duplex, and 100Mbs Full-Duplex). Auto-Negotiation selects the highest performance protocol based
on the advertised ability of the Link Partner. Control the Auto-Negotiation function within the TLK111 by:
1. Internal register access, or
2. Configuring the AN_EN, AN_1 and AN_0 pins
The state of the AN_EN, AN_0 and AN_1 pins determine whether the TLK111 is forced into a specific
mode, or if Auto-Negotiation advertises a specific ability (or set of abilities) as given in Table 3-1. These
pins allow configuration options to be selected without requiring internal register access. The state of
AN_EN, AN_0 and AN_1, upon power-up/reset, determines the state of bits [8:5] of the ANAR register
(0x04h).
Internal register access controls the Auto-Negotiation function, as defined by the IEEE 802.3u
specification. For further detail regarding Auto-Negotiation, see Clause 28 of the IEEE 802.3u
specification.
AN_EN
0
0
0
0
AN_EN
1
1
1
1
Table 3-1. Auto-Negotiation Modes
AN_1
0
0
1
1
AN_1
0
0
1
1
AN_0
0
1
0
1
AN_0
0
1
0
1
Forced Mode
10Base-T, Half-Duplex
10Base-T, Full-Duplex
100Base-TX, Half-Duplex
100Base-TX, Full-Duplex
Advertised Mode
10Base-T, Half or Full-Duplex
100Base-TX, Half or Full-Duplex
10Base-T, Half Duplex
100Base-TX, Half Duplex
10Base-T, Half or Full-Duplex
100Base-TX, Half or Full-Duplex
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Hardware Configuration
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