TLK111_14 Datasheet, PDF (4/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
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2 Pin Descriptions
The TLK111 pins fall into the following interface categories (subsequent sections describe each interface):
• Serial Management Interface
• MAC Data Interface
• Clock Interface
• LED Interface
• JTAG Interface
• Reset and Power Down
• Bootstrap Configuration Inputs
• 10/100Mbs PMD Interface
• Special Connect Pins
• Power and Ground pins
Note: Configuration pin option. See Section 3.1 for Jumper Definitions.
The definitions below define the functionality of each pin.
Type: I Input
Type: O Output
Type: I/O Input/Output
Type: OD
Open Drain
Type: PD, PU Internal Pulldown/Pullup
Type: S
Configuration Pin (All configuration pins have weak internal
pullups or pulldowns. Use an external 2.2kΩ resistor if you
need a different default value. See Section 3.1 for details.)
2.1 Pin Layout
PFBIN2
37
RX_CLK
38
RX_DV / MII_MODE
39
CRS/CRS_DV / LED_CFG
40
RX_ER / AMDIX_EN
41
COL / PHYAD0
42
RXD_0 / PHYAD1
43
RXD_1 / PHYAD2
44
RXD_2 / PHYAD3
45
RXD_3 / PHYAD4
46
IOGND
47
VDD_IO
48
24
RBIAS
23
PFBOUT
22
AVDD33
21
SW_STRAP
20
RESERVED
19
AGND
18
PFBIN1
17
TD +
16
TD –
15
AGND
14
RD +
13
RD –
Figure 2-1. TLK111 PIN DIAGRAM, TOP VIEW
This document describes signals that take on different names depending on configuration. In such cases,
the different names are placed together and separated by slash (/) characters. For example, "RXD_3 /
PHYAD4". Active low signals are represented by overbars.
.
4
Pin Descriptions
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