TLK111_14 Datasheet, PDF (64/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
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• REGCR [15:14] = 11: A read/write to ADDAR operates on the register within the extended register set
selected (pointed to) by the value in the address register. After that access is complete, for write
accesses only, the value in the address register is incremented. For read accesses, the value of the
address register remains unchanged.
8.1.13.1 Register Control Register (REGCR)
This register is the MDIO Manageable MMD access control. In general, register REGCR (4:0) is the
device address DEVAD that directs any accesses of the ADDAR (0x000E) register to the appropriate
MMD. REGCR also contains selection bits for auto increment of the data register. This register contains
the device address to be written to access the extended registers. Write 0x1F into bits 4:0 of this register.
REGCR also contains selection bits (15:14) for the address auto-increment mode of ADDAR.
Table 8-16. Register Control Register (REGCR), address 0x000D
BIT
15:14
13:5
4:0
BIT NAME
Function
RESERVED
DEVAD
DEFAULT
0, RW
0, RO
0, RW
DESCRIPTION
00 = Address
01 = Data, no post increment
10 = Data, post increment on read and write
11 = Data, post increment on write only
RESERVED: Writes ignored, read as 0.
Device Address: In general, these bits [4:0] are the device address DEVAD that directs any
accesses of ADDAR register (0x000E) to the appropriate MMD. Specifically, the TLK111 uses the
vendor specific DEVAD [4:0] = “11111” for accesses. All accesses through registers REGCR and
ADDAR should use this DEVAD. Transactions with other DEVAD are ignored.
8.1.13.2 Address or Data Register (ADDAR)
This register is the address/data MMD register. ADDAR is used in conjunction with REGCR register
(0x000D) to provide the access by indirect read/write mechanism to the extended register set.
BIT BIT NAME
15:0 Addr/data
Table 8-17. Data Register (ADDAR), address 0x000E
DEFAULT
0, RW
DESCRIPTION
If REGCR register 15:14 = 00, holds the MMD DEVAD's address register, otherwise holds the
MMD DEVAD's data register
8.1.14 Fast Link Down Status Register
BIT BIT NAME
15:9 RESERVED
Fast Link
8:4
Down
Status[4:0]
3:0 RESERVED
Table 8-18. Fast Link Down Status (FLDS), address 0x000F
DEFAULT
0, RO
0, RO, LH
0, RO
DESCRIPTION
RESERVED
Status Registers that latch high each time a given Fast Link Down mode is activated and causes a
link drop (assuming this criterion was enabled):
Bit 4 Descrambler Loss Sync
Bit 3 RX Errors
Bit 2 MLT3 Errors
Bit 1 SNR level
Bit 0 Signal/Energy Lost
RESERVED
64
Register Block
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