TLK111_14 Datasheet, PDF (69/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
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SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
Table 8-22. MII Interrupt Status Register 2 (MISR2), address 0x0013 (continued)
BIT
NAME
5 Page Rec EN
4 Loopback FIFO OF/UF EN
3 MDI Crossover Changed EN
2 Sleep Mode Event EN
1 Polarity Changed EN
0 Jabber Detect EN
DEFAULT
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
DESCRIPTION
Enable Interrupt on page receive event
Enable Interrupt on loopback FIFO overflow/underflow event
Enable Interrupt on change of MDI/X status
Enable Interrupt sleep mode event
Enable Interrupt on change of polarity status
Enable Interrupt on Jabber detection event
8.1.19 False Carrier Sense Counter Register (FCSCR)
This counter provides information required to implement the "False Carriers" attribute within the MAU
managed object class of Clause 30 of the IEEE 802.3u specification.
Table 8-23. False Carrier Sense Counter Register (FCSCR), address 0x0014
BIT NAME
15:8 RESERVED
7:0 FCSCNT
DEFAULT
0000 0000, RO
0,RO / COR
DESCRIPTION
RESERVED: Writes ignored, read as 0
False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This counter stops when it
reaches its maximum count (FFh). When the counter exceeds half full (7Fh), an interrupt
event is generated. This register is cleared on read.
8.1.20 Receiver Error Counter Register (RECR)
This counter provides information required to implement the "Symbol Error During Carrier" attribute within
the PHY managed object class of Clause 30 of the IEEE 802.3u specification.
Table 8-24. Receiver Error Counter Register (RECR), address 0x0015
BIT
BIT NAME
15:0 RX Error Count
DEFAULT
DESCRIPTION
0, RO, / COR RX_ER Counter:
When a valid carrier is present (only while RXDV is set), and there is at least one occurrence of
an invalid data symbol, this 16-bit counter increments for each receive error detected. The
RX_ER counter does not count in MII loopback mode. The counter stops when it reaches its
maximum count of FFFFh. When the counter exceeds half-full (7FFFh), an interrupt is
generated. This register is cleared on read.
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