TLK111_14 Datasheet, PDF (103/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
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SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision Initial (August 2013) to Revision A
Page
• Changed "VDD33_IO" to "VDD_IO" ............................................................................................... 4
• Deleted "SNI_mode" ................................................................................................................. 4
• Changed "200ms" to "200µs" (typo correction) ................................................................................. 15
• Added Signal Detect feature description ........................................................................................ 37
• Added recommended fiber transceiver to application diagram ............................................................... 43
• Added note to application diagram, "place resisitors and capacitors close to fiber transceiver" ......................... 43
• Added Power Back Off Control Register (0AEh) ............................................................................... 44
• Registers 0010h - 001Fh moved from extended-addressing space to direct-addressing space ........................ 50
• Changed default value for MDL_REV from 0001 to 0010 .................................................................... 53
• Changed Default value of interrupt-polarity bit from 0 to 1 ................................................................... 66
• Updated RMII Control and Status Register bit 4 description ................................................................. 71
• Changed names for bits 5 and 6 from "FEF ... Enable" to "FEF ... Disable" ............................................... 76
• Added maximum storage temperature .......................................................................................... 84
• Added DC characteristics table for SD_IN ...................................................................................... 85
• Changed "... stable for minimum of 1ms ..." to "... stable for minimum of 1µs ..." (typo correction) ..................... 88
• Changed titles, "100Base-TX ... Timing" to "100Base-TX / FX ... Timing" .................................................. 90
Revision History
Changes from Revision Initial (November 2013) to Revision B
Page
• Changed "Low Power Consumption: <205mW PHY and 275mW with Center Tap (Typical)" to "Low Power
Consumption: <126mW PHY and 200mW with Center Tap (Typical, dual supplies)" ...................................... 1
• Changed "MII and RMII Interfaces" to "MII and RMII Capabilities" ........................................................... 1
• Changed "Error-Free Operation up to 150 Meters Under Typical Conditions" to "Error-Free 100Base-T
Operation up to 150 Meters Under Typical Conditions Error-Free 10Base-T Operation up to 300 Meters Under
Typical Conditions" .................................................................................................................. 1
• Added bit 10, Fast Link Down Mode enable, Drop the link based on descrambler link loss, adusted description
of bits 3:0 to reflect 5 options instead of 4 ...................................................................................... 63
• Deleted " Allow the system to reset the PHY using register access." ....................................................... 75
• Added operating conditions for single and dual supplies ..................................................................... 84
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Electrical Specifications 103