TLK111_14 Datasheet, PDF (70/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
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8.1.21 BIST Control Register (BISCR)
This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo
Random Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of
the exact loopback point in the signal chain is also done in this register.
Table 8-25. BIST Control Register (BISCR), address 0x0016
BIT NAME
15 RESERVED
14 PRBS Count Mode
13 Generate PRBS Packets
12 Packet Generation Enable
11 PRBS Checker Lock
10 PRBS Checker Sync Loss
9 Packet Gen Status
8 Power Mode
7 RESERVED
6 Transmit in MII Loopback
5 RESERVED
4:0 Loopback Mode
DEFAULT
0, RO
0, RW
0, RW
0, RW
0,RO
0,RO,LH
0,RO
0,RO
0, RO
0, RW
0, RO
0, RW
DESCRIPTION
RESERVED: Writes ignored, read as 0
PRBS Single/Continues Mode:
1 = Continuous mode, the PRBS counters reaches max count value, pulse is
generated and counter starts counting from zero again.
0 = Single mode, When BIST Error Counter reaches its max value, PRBS checker
stops counting.
Generated PRBS Packets:
1 = When packet generator is enabled, generate continuous packets with PRBS
data. When packet generator is disabled, PRBS checker is still enabled.
0 = When packet generator is enabled, generate single packet with constant data.
PRBS gen/check is disabled.
Packet Generation Enable:
1 = Enable packet generation with PRBS data
0 = Disable packet generator
PRBS Checker Lock Indication:
1 = PRBS checker is locked and synced on received bit stream
0 = PRBS checker is not locked
PRBS Checker Sync Loss Indication:
1 = PRBS checker lose sync on received bit stream – This is an error indication
0 = PRBS checker is not locked
Packet Generator Status Indication:
1 = Packet Generator is active and generate packets
0 = Packet Generator is off
Sleep Mode Indication:
1 = Indicate that the PHY is in normal power mode
0 = Indicate that the PHY is in one of the sleep modes, either active or passive
RESERVED: Writes ignored, read as 0.
Transmit Data in MII Loop-back Mode (valid only at 100BT):
1 = Enable transmission of the data from the MAC received on the TX pins to the
line in parallel to the MII loopback to RX pins. This bit may be set only in MII
Loopback mode – setting bit 14 in BMCR register (0x0000).
0 = Data is not transmitted to the line in MII loopback
RESERVED: Must be 0
Loop-back Mode Select:
The PHY provides several options for Loopback that test and verify various functional
blocks within the PHY. Enabling loopback mode allows in-circuit testing of the TLK111
digital and analog data path
Near-end Loopback
00001 = PCS Input Loopback
00010 = PCS Output Loopback
00100 = Digital Loopback
01000 = Analog Loopback (requires 100Ω termination)
Far-end Loopback:
10000 = Reverse Loopback
70
Register Block
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