TLK111_14 Datasheet, PDF (17/110 Pages) Texas Instruments – PHYTER® Industrial Temperature 10/100Mbs Ethernet Physical Layer Transceiver

TLK111
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SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014
3.10 Multi-Configurable LED (MLED)
In addition, the TLK111 supports by register access a multi-configurable LED (MLED). The MLED by
default is not activated; by register access it can be routed through either the 3 LED pins 26-28 or the
COL pin, allowing support of 4 LEDS. When MLED is routed to the COL pin, the COL functionality is
disabled. REG 0x0025 (MLEDCR Register) controls the MLED routing and configurations. The different
MLED modes are configured by bits [6:3] as described in Table 3-4.
(bit 6:3)
0x0
0x1
0x2
0x3
0x4
0x5
Table 3-4. MLED Mode Select
Mode
Link OK
RX/TX Activity
TX Activity
RX Activity
Collision
LED Speed: High for 100 Base TX
(bit 6:3)
0x6
0x7
0x8
0x9
0xA
Mode
LED Speed: High for 10 Base TX
Full Duplex
Link OK / Blink on TX/RX Activity
Active stretch signal
MI_LINK (100BT+FD)
3.11 Loopback Functionality
The TLK111 provides several options for Loopback that test and verify various functional blocks within the
PHY. Enabling loopback mode allows in-circuit testing of the TLK111 digital and analog data path.
Generally, the TLK111 may be configured to one of the Near-end loopback modes or to the Far-end
(reverse) loopback.
3.11.1 Near-End Loopback
Near-end loopback provides the ability to loop the transmitted data back to the receiver via the digital or
analog circuitry. The point at which the signal is looped back is selected using loopback control bits with
several options being provided. Figure 3-7 shows the PHY near-end loopback functionality.
MAC/
Switch
PCS Loopback
Analog Loopback
M
I
PCS
I
Signal
Process
PHY Digital
PHY
AFE
1
2
3
4
XFMR
5
6
7
8
MII Loopback
Digital Loopback
External Loopback
Figure 3-7. Block Diagram, Near-End Loopback Mode
The Near-end Loopback mode is selected by setting the respective bit in the BIST Control Register
(BISCR), MII register address 0x0016. MII loopback can be selected by using the BMCR register at
address 0x0000, bit [14].
The Near-end Loopback can be selected according to the following:
• Reg 0x0000, Bit [14]: MII Loopback
• Reg 0x0016, Bit [0]: PCS input Loopback
• Reg 0x0016, Bit [1]: PCS output Loopback
• Reg 0x0016, Bit [2]: Digital Loopback
• Reg 0x0016, Bit [3]: Analog Loopback
Table 3-5 describes the available operational modes for each loop mode:
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Hardware Configuration
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