SM320F28335PTPMEP Datasheet, PDF (95/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
Table 4-18. GPIO-C Mux Peripheral Selection Matrix
REGISTER BITS
GPCDIR
GPCDAT
GPCSET
GPCCLR
GPCTOGGLE
no qual
0
1
2
3
4
5
6
7
no qual
8
9
10
11
12
13
14
15
no qual
16
17
18
19
20
21
22
23
GPCMUX1
1, 0
3, 2
5, 4
7, 6
9, 8
11, 10
13, 12
15, 14
17, 16
19, 18
21, 20
23, 22
25, 24
27, 26
29, 28
31, 30
GPCMUX2
1, 0
3, 2
5, 4
7, 6
9, 8
11, 10
13, 12
15, 14
PERIPHERAL SELECTION
GPIOx or PER1
GPCMUX1 = 0, 0 or 0, 1
GPIO64 (I/O)
GPIO65 (I/O)
GPIO66 (I/O)
GPIO67 (I/O)
GPIO68 (I/O)
GPIO69 (I/O)
GPIO70 (I/O)
GPIO71 (I/O)
GPIO72 (I/O)
GPIO73 (I/O)
GPIO74 (I/O)
GPIO75 (I/O)
GPIO76 (I/O)
GPIO77 (I/O)
GPIO78 (I/O)
GPIO79 (I/O)
GPCMUX2 = 0, 0 or 0, 1
GPIO80 (I/O)
GPIO81 (I/O)
GPIO82 (I/O)
GPIO83 (I/O)
GPIO84 (I/O)
GPIO85 (I/O)
GPIO86 (I/O)
GPIO87 (I/O)
PER2 or PER3
GPCMUX1 = 1, 0 or 1, 1
XD15 (I/O)
XD14 (I/O)
XD13 (I/O)
XD12 (I/O)
XD11 (I/O)
XD10 (I/O)
XD9 (I/O)
XD8 (I/O)
XD7 (I/O)
XD6 (I/O)
XD5 (I/O)
XD4 (I/O)
XD3 (I/O)
XD2 (I/O)
XD1 (I/O)
XD0 (I/O)
GPCMUX2 = 1, 0 or 1, 1
XA8 (O)
XA9 (O)
XA10 (O)
XA11 (O)
XA12 (O)
XA13 (O)
XA14 (O)
XA15 (O)
The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from
four choices:
• Synchronization To SYSCLKOUT Only (GPxQSEL1/2=0, 0): This is the default mode of all GPIO pins
at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
• Qualification Using Sampling Window (GPxQSEL1/2=0, 1 and 1, 0): In this mode the input signal, after
synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before
the input is allowed to change.
Copyright © 2009–2012, Texas Instruments Incorporated
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Peripherals
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