SM320F28335PTPMEP Datasheet, PDF (92/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
www.ti.com
The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame
1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-15 shows the GPIO
register mapping.
Table 4-15. GPIO Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPACTRL
0x6F80
2
GPIO A Control Register (GPIO0 to 31)
GPAQSEL1
0x6F82
2
GPIO A Qualifier Select 1 Register (GPIO0 to 15)
GPAQSEL2
0x6F84
2
GPIO A Qualifier Select 2 Register (GPIO16 to 31)
GPAMUX1
0x6F86
2
GPIO A MUX 1 Register (GPIO0 to 15)
GPAMUX2
0x6F88
2
GPIO A MUX 2 Register (GPIO16 to 31)
GPADIR
0x6F8A
2
GPIO A Direction Register (GPIO0 to 31)
GPAPUD
0x6F8C
2
GPIO A Pull Up Disable Register (GPIO0 to 31)
Reserved
0x6F8E – 0x6F8F
2
GPBCTRL
0x6F90
2
GPIO B Control Register (GPIO32 to 63)
GPBQSEL1
0x6F92
2
GPIO B Qualifier Select 1 Register (GPIO32 to 47)
GPBQSEL2
0x6F94
2
GPIOB Qualifier Select 2 Register (GPIO48 to 63)
GPBMUX1
0x6F96
2
GPIO B MUX 1 Register (GPIO32 to 47)
GPBMUX2
0x6F98
2
GPIO B MUX 2 Register (GPIO48 to 63)
GPBDIR
0x6F9A
2
GPIO B Direction Register (GPIO32 to 63)
GPBPUD
0x6F9C
2
GPIO B Pull Up Disable Register (GPIO32 to 63)
Reserved
0x6F9E – 0x6FA5
8
GPCMUX1
0x6FA6
2
GPIO C MUX1 Register (GPIO64 to 79)
GPCMUX2
0x6FA8
2
GPIO C MUX2 Register (GPIO80 to 87)
GPCDIR
0x6FAA
2
GPIO C Direction Register (GPIO64 to 87)
GPCPUD
0x6FAC
2
GPIO C Pull Up Disable Register (GPIO64 to 87)
Reserved
0x6FAE – 0x6FBF
18
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPADAT
0x6FC0
2
GPIO A Data Register (GPIO0 to 31)
GPASET
0x6FC2
2
GPIO A Data Set Register (GPIO0 to 31)
GPACLEAR
0x6FC4
2
GPIO A Data Clear Register (GPIO0 to 31)
GPATOGGLE
0x6FC6
2
GPIO A Data Toggle Register (GPIO0 to 31)
GPBDAT
0x6FC8
2
GPIO B Data Register (GPIO32 to 63)
GPBSET
0x6FCA
2
GPIO B Data Set Register (GPIO32 to 63)
GPBCLEAR
0x6FCC
2
GPIO B Data Clear Register (GPIO32 to 63)
GPBTOGGLE
0x6FCE
2
GPIOB Data Toggle Register (GPIO32 to 63)
GPCDAT
0x6FD0
2
GPIO C Data Register (GPIO64 to 87)
GPCSET
0x6FD2
2
GPIO C Data Set Register (GPIO64 to 87)
GPCCLEAR
0x6FD4
2
GPIO C Data Clear Register (GPIO64 to 87)
GPCTOGGLE
0x6FD6
2
GPIO C Data Toggle Register (GPIO64 to 87)
Reserved
0x6FD8 0x6FDF
8
GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
GPIOXINT1SEL
0x6FE0
1
XINT1 GPIO Input Select Register (GPIO0 to 31)
GPIOXINT2SEL
0x6FE1
1
XINT2 GPIO Input Select Register (GPIO0 to 31)
GPIOXNMISEL
0x6FE2
1
XNMI GPIO Input Select Register (GPIO0 to 31)
GPIOXINT3SEL
0x6FE3
1
XINT3 GPIO Input Select Register (GPIO32 to 63)
GPIOXINT4SEL
0x6FE4
1
XINT4 GPIO Input Select Register (GPIO32 to 63)
GPIOXINT5SEL
0x6FE5
1
XINT5 GPIO Input Select Register (GPIO32 to 63)
92
Peripherals
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F28335-EP