SM320F28335PTPMEP Datasheet, PDF (50/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
GPIO
Mux
Clock Enables
LSPCLK
System
Control
Register
LOSPCP
I/O
Peripheral
SPI-A, SCI-A/B/C
Registers
Clock Enables
I2C-A
Clock Enables
/2
I/O
eCAN-A/B
Clock Enables
Peripheral
Registers
I/O
EPWM1/../6, HRPWM1/../6, Peripheral
ECAP1/../6, EQEP1/2 Registers
Clock Enables
LSPCLK
LOSPCP
I/O
Peripheral
McBSP-A/B
Registers
Clock Enables
HSPCLK
HISPCP
C28x Core
SYSCLKOUT
Bridge
Bridge
Bridge
16 Channels
12-Bit ADC
ADC
Registers
Bridge
www.ti.com
CLKIN
Result
Registers
Clock Enables
DMA
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT). See Figure 3-7 for an illustration of how CLKIN is derived.
Figure 3-6. Clock and Reset Domains
NOTE
There is a 2-SYSCLKOUT cycle delay from when the write to PCLKCR0/1/2 registers
(enables peripheral clocks) occurs to when the action is valid. This delay must be taken into
account before attempting to access the peripheral configuration registers.
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-13.
50
Functional Overview
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