SM320F28335PTPMEP Datasheet, PDF (31/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
3 Functional Overview
M0 SARAM 1Kx16
(0-Wait)
M1 SARAM 1Kx16
(0-Wait)
Boot ROM
8K x 16
L0 SARAM 4K x 16
(0-Wait, Dual Map)
L1 SARAM 4K x 16
(0-Wait, Dual Map)
L2 SARAM 4K x 16
(0-Wait, Dual Map)
L3 SARAM 4K x 16
(0-Wait, Dual Map)
L4 SARAM 4K x 16
(0-W Data, 1-W Prog)
L5 SARAM 4K x 16
(0-W Data, 1-W Prog)
L6 SARAM 4K x 16
(0-W Data, 1-W Prog)
L7 SARAM 4K x 16
(0-W Data, 1-W Prog)
Memory Bus
XD31:0
88 GPIOs
GPIO
MUX
XHOLDA
XHOLD
XREADY
XR/W
XZCS0
XZCS7
XZCS6
XWE0
XA0/XWE1
XA19:1
XCLKOUT
XRD
88 GPIOs
A7:0
B7:0
REFIN
GPIO
MUX
12-Bit
ADC
2-S/H
8 External Interrupts
DMA Bus
SPRS581D – JUNE 2009 – REVISED MAY 2012
OTP 1K x 16
Code
Security
Module
PSWD
Flash
256K x 16
8 Sectors
Pump
Flash
Wrapper
TEST2
TEST1
FPU
32-bit CPU
(150 MHZ @ 1.9 V)
(100 MHz @ 1.8 V)
DMA
6 Ch
CPU Timer 0
CPU Timer 1
CPU Timer 2
PIE
(Interrupts)
OSC,
PLL,
LPM,
WD
TCK
TDI
TMS
TDO
TRST
EMU0
EMU1
XCLKIN
X1
X2
XRS
Memory Bus
XINTF
16-bit peripheral bus
32-bit peripheral bus
(DMA accessible)
32-bit peripheral bus
FIFO
(16 Levels)
SCI-A/B/C
FIFO
(16 Levels)
SPI-A
FIFO
(16 Levels)
I2C
McBSP-A/B
EPWM-1/../6
HRPWM-1/../6
ECAP-1/../6 EQEP-1/2
CAN-A/B
(32-mbox)
Secure zone
GPIO MUX
88 GPIOs
Figure 3-1. Functional Block Diagram
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F28335-EP
Functional Overview
31