SM320F28335PTPMEP Datasheet, PDF (41/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn)
The device segregates peripherals into three sections. The mapping of peripherals is as follows:
PF0: PIE:
PIE Interrupt Enable and Control Registers Plus PIE Vector Table
Flash:
XINTF:
Flash Waitstate Registers
External Interface Registers
DMA
Timers:
CSM:
DMA Registers
CPU-Timers 0, 1, 2 Registers
Code Security Module KEY Registers
ADC:
PF1: eCAN:
ADC Result Registers (dual-mapped)
eCAN Mailbox and Control Registers
GPIO:
ePWM:
eCAP:
GPIO MUX Configuration and Control Registers
Enhanced Pulse Width Modulator Module and Registers (dual mapped)
Enhanced Capture Module and Registers
eQEP:
PF2: SYS:
Enhanced Quadrature Encoder Pulse Module and Registers
System Control Registers
SCI:
SPI:
ADC:
Serial Communications Interface (SCI) Control and RX/TX Registers
Serial Port Interface (SPI) Control and RX/TX Registers
ADC Status, Control, and Result Register
I2C:
XINT
Inter-Integrated Circuit Module and Registers
External Interrupt Registers
PF3: McBSP
ePWM:
Multichannel Buffered Serial Port Registers
Enhanced Pulse Width Modulator Module and Registers (dual mapped)
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This
enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins
are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal
mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter
unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power
modes.
3.2.19 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is
reserved for Real-Time OS (RTOS)/BIOS applications. It is connected to INT14 of the CPU. If DSP/BIOS
is not being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be
connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.
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Functional Overview
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