SM320F28335PTPMEP Datasheet, PDF (118/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
www.ti.com
Table 6-17. HALT Mode Timing Requirements
t_w(WAKE-GPIO)
Pulse duration, GPIO wake-up signal
t_w(WAKE-XRS)
Pulse duration, XRS wakeup signal
(1) See Table 6-10 for an explanation of t_oscst.
MIN
t_oscst + 2t_c(OSCCLK) ⁽¹⁾
t_oscst + 8t_c(OSCCLK)
NOM
MAX
Table 6-18. HALT Mode Switching Characteristics
t_d(IDLE-XCOL)
t_p
t_d(WAKE-HALT)
PARAMETER
Delay time, IDLE instruction executed to XCLKOUT
low
PLL lock-up time
Delay time, PLL lock to program execution resume
• Wake up from flash
– Flash module in sleep state
• Wake up from SARAM
MIN
32t_c(SCO)
TYP
MAX
45t_c(SCO)
131072t_c(OSCCLK)
1125t_c(SCO)
35t_c(SCO)
UNIT
cycles
cycles
UNIT
cycles
cycles
cycles
cycles
118 Electrical Specifications
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