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SM320F28335PTPMEP Datasheet, PDF (109/167 Pages) Texas Instruments – Digital Signal Controller (DSC)
SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
6.7 Clock Requirements and Characteristics
Table 6-5. Input Clock Frequency
PARAMETER
Resonator (X1/X2)
fx
Input clock frequency
Crystal (X1/X2)
External oscillator/clock
source (XCLKIN or X1 pin)
150-MHz device
100-MHz device
fl
Limp mode SYSCLKOUT frequency range (with /2 enabled)
MIN TYP MAX UNIT
20
35
20
35
MHz
4
150
4
100
1-5
MHz
Table 6-6. XCLKIN Timing Requirements - PLL Enabled
NO.
C8
C9
C10
C11
C12
tc(CI)
tf(CI)
tr(CI)
tw(CIL)
tw(CIH)
Cycle time, XCLKIN
Fall time, XCLKIN(1)
Rise time, XCLKIN(1)
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) (1)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) (1)
(1) This applies to the X1 pin also.
MIN
33.3
45
45
MAX
200
6
6
55
55
UNIT
ns
ns
ns
%
%
Table 6-7. XCLKIN Timing Requirements - PLL Disabled
NO.
C8 tc(CI)
C9 tf(CI)
C10 tr(CI)
C11
C12
tw(CIL)
tw(CIH)
Cycle time, XCLKIN
150-MHz device
Fall time, XCLKIN(1)
100-MHz device
Up to 30 MHz
Rise time, XCLKIN(1)
30 MHz to 150 MHz
Up to 30 MHz
30 MHz to 150 MHz
Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) (1)
Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) (1)
(1) This applies to the X1 pin also.
MIN
6.67
10
45
45
The possible configuration modes are shown in Table 3-16.
MAX
250
250
6
2
6
2
55
55
UNIT
ns
ns
ns
ns
ns
%
%
Table 6-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1) (2)
NO.
PARAMETER
MIN
C1 tc(XCO)
Cycle time, XCLKOUT
150-MHz device
6.67
100-MHz device
10
C3 tf(XCO)
C4 tr(XCO)
C5 tw(XCOL)
C6 tw(XCOH)
tp
Fall time, XCLKOUT
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
PLL lock time
H–2
H–2
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5tc(XCO)
(3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.
TYP
2
2
MAX
UNIT
ns
H+2
H+2
131072tc(OSCCLK) (3)
ns
ns
ns
ns
cycles
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Electrical Specifications 109