SM320F28335PTPMEP Datasheet, PDF (46/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
www.ti.com
DMA
XINT3
Interrupt Control
XINT3CR(15:0)
Latch
DMA
GPIOXINT3SEL(4:0)
XINT4
Interrupt Control
XINT4CR(15:0)
Latch
INT1
to
INT12
PIE
C28
Core
DMA
GPIOXINT4SEL(4:0)
XINT5
Interrupt Control
XINT5CR(15:0)
Latch
DMA
GPIOXINT5SEL(4:0)
XINT6
Interrupt Control
XINT6CR(15:0)
Latch
DMA
GPIOXINT6SEL(4:0)
XINT7
Interrupt Control
XINT7CR(15:0)
Latch
GPIO32.int
GPIO63.int
GPIO
Mux
GPIOXINT7SEL(4:0)
Figure 3-4. External Interrupts
Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8
interrupts per group equals 96 possible interrupts. On the F28335, 58 of these are used by peripherals as
shown in Table 3-10.
The TRAP #VectorNumber instruction transfers program control to the interrupt service routine
corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address
pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore,
TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior.
When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service
routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector
from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth.
46
Functional Overview
Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): SM320F28335-EP