SM320F28335PTPMEP Datasheet, PDF (81/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
6200h
623Fh
6240h
627Fh
6280h
62BFh
62C0h
62FFh
eCAN-B Memory (512 Bytes)
Control and Status Registers
Local Acceptance Masks (LAM)
(32 × 32-Bit RAM)
Message Object Time Stamps (MOTS)
(32 × 32-Bit RAM)
Message Object Time-Out (MOTO)
(32 × 32-Bit RAM)
6300h−6307h
6308h−630Fh
6310h−6317h
6318h−631Fh
6320h−6327h
eCAN-B Memory RAM (512 Bytes)
Mailbox 0
Mailbox 1
Mailbox 2
Mailbox 3
Mailbox 4
eCAN-B Control and Status Registers
Mailbox Enable − CANME
Mailbox Direction − CANMD
Transmission Request Set − CANTRS
Transmission Request Reset − CANTRR
Transmission Acknowledge − CANTA
Abort Acknowledge − CANAA
Received Message Pending − CANRMP
Received Message Lost − CANRML
Remote Frame Pending − CANRFP
Global Acceptance Mask − CANGAM
Master Control − CANMC
Bit-Timing Configuration − CANBTC
Error and Status − CANES
Transmit Error Counter − CANTEC
Receive Error Counter − CANREC
Global Interrupt Flag 0 − CANGIF0
Global Interrupt Mask − CANGIM
Global Interrupt Flag 1 − CANGIF1
Mailbox Interrupt Mask − CANMIM
Mailbox Interrupt Level − CANMIL
Overwrite Protection Control − CANOPC
TX I/O Control − CANTIOC
RX I/O Control − CANRIOC
Time Stamp Counter − CANTSC
Time-Out Control − CANTOC
Time-Out Status − CANTOS
63E0h−63E7h
63E8h−63EFh
63F0h−63F7h
63F8h−63FFh
Mailbox 28
Mailbox 29
Mailbox 30
Mailbox 31
Reserved
63E8h−63E9h
63EAh−63EBh
63ECh−63EDh
63EEh−63EFh
Message Mailbox (16 Bytes)
Message Identifier − MSGID
Message Control − MSGCTRL
Message Data Low − MDL
Message Data High − MDH
Figure 4-14. eCAN-B Memory Map
The CAN registers listed in Table 4-9 are used by the CPU to configure and control the CAN controller
and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM
can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary.
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