SM320F28335PTPMEP Datasheet, PDF (152/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
www.ti.com
6.16 Multichannel Buffered Serial Port (McBSP) Timing
6.16.1 McBSP Transmit and Receive Timing
Table 6-54. McBSP Timing Requirements^{(1) (2)}
NO.
MIN
MAX UNIT
McBSP module clock (CLKG, CLKX, CLKR) range
1
kHz
25⁽³⁾ MHz
McBSP module cycle time (CLKG, CLKX, CLKR)
range
40
ns
1 ms
M11
M12
M13
M14
M15
t_c(CKRX)
t_w(CKRX)
t_r(CKRX)
t_f(CKRX)
t_su(FRH-CKRL)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
Fall time, CLKR/X
Setup time, external FSR high before CLKR low
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
2P
P–7
18
2
ns
ns
7 ns
7 ns
ns
M16
t_h(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
CLKR ext
0
ns
6
M17
t_su(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int
CLKR ext
18
ns
2
M18
t_h(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
CLKR ext
0
ns
6
M19
t_su(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int
CLKX ext
18
ns
2
M20
t_h(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int
CLKX ext
0
ns
6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
CLKSRG
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = ^{(1 ) CLKGDV)} CLKSRG can be LSPCLK, CLKX,
CLKR as source. CLKSRG ≤ (SYSCLKOUT/2). McBSP performance is limited by I/O buffer switching speed.
(3) Internal clock prescalers must be adjusted such that the McBSP clock (CLKG, CLKX, CLKR) speeds are not greater than the I/O buffer
speed limit (25 MHz).
Table 6-55. McBSP Switching Characteristics^{(1) (2)}
NO.
M1
M2
M3
M4
t_c(CKRX)
t_w(CKRXH)
t_w(CKRXL)
t_d(CKRH-FRV)
M5
t_d(CKXH-FXV)
M6
t_{dis(CKXH-DXHZ)}
PARAMETER
Cycle time, CLKR/X
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
Delay time, CLKR high to internal FSR valid
Delay time, CLKX high to internal FSX valid
Disable time, CLKX high to DX high impedance
following last data bit
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
MIN
2P
D-5 ⁽³⁾
C-5 ⁽³⁾
0
3
0
3
MAX
D+5 ⁽³⁾
C+5 ⁽³⁾
4
27
4
27
8
14
UNIT
ns
ns
ns
ns
ns
ns
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns.
(3) C=CLKRX low pulse width = P
D=CLKRX high pulse width = P
152 Electrical Specifications
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