SM320F28335PTPMEP Datasheet, PDF (58/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
SPRS581D – JUNE 2009 – REVISED MAY 2012
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4.2 32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the devices (CPU-TIMER0/1/2).
Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0 and CPU-Timer 1 can be used in user applications.
These timers are different from the timers that are present in the ePWM modules.
NOTE
NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the
application.
Reset
Timer Reload
SYSCLKOUT
TCR.4
(Timer Start Status)
TINT
16-Bit Timer Divide-Down
TDDRH:TDDR
16-Bit Prescale Counter
PSCH:PSC
Borrow
Figure 4-2. CPU-Timers
32-Bit Timer Period
PRDH:PRD
32-Bit Counter
TIMH:TIM
Borrow
The timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in Figure 4-3.
INT1
to
INT12
PIE
TINT0
CPU-TIMER 0
28x
CPU
INT13
TINT1
CPU-TIMER 1
INT14
TINT2
XINT13
CPU-TIMER 2
(Reserved for DSP/BIOS)
A. The timer registers are connected to the memory bus of the C28x processor.
B. The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4-3. CPU-Timer Interrupt Signals and Output Signal
The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the
value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the
C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The
registers listed in Table 4-1 are used to configure the timers.
58
Peripherals
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