SM320F28335PTPMEP Datasheet, PDF (139/167 Pages) Texas Instruments – Digital Signal Controller (DSC)

SM320F28335-EP
www.ti.com
SPRS581D – JUNE 2009 – REVISED MAY 2012
(A) (B)
XCLKOUT = XTIMCLK
XCLKOUT = 1/2 XTIMCLK
XZCS0, XZCS6, XZCS7
Lead
t_{d(XCOH-XZCSL)}
WS (Async)
Active
Trail
(C)
t_{d(XCOHL-XZCSH)}
XA[0:19]
XRD
XWE0, XWE1^(D)
XR/W
XD[0:31], XD[0:15]
XREADY(Asynch)
t_d(XCOH-XA)
t_{d(XCOHL-XRDL)}
t_su(XD)XRD
t_a(XRD)
t_{d(XCOHL-XRDH)}
t_a(A)
DIN
t_h(XD)XRD
t_{su(XRDYasynchL)XCOHL}
t_{e(XRDYasynchH)}
t_{h(XRDYasynchL)}
t_{h(XRDYasynchH)XZCSH}
t_{su(XRDYasynchH)XCOHL}
(E)
(F)
Legend:
= Don’t care. Signal can be high or low during this time.
A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus except XA0, which
remains high. This includes alignment cycles.
D. XWE1 is valid only in 32-bit data bus mode. In 16-bit mode, this signal is XA0.
E. For each sample, setup time from the beginning of the access can be calculated as:
E = (XRDLEAD + XRDACTIVE -3 +n) t_c(XTIM) – t_{su(XRDYasynchL)XCOHL} where n is the sample number: n = 1, 2, 3, and
so forth.
F. Reference for the first sample is with respect to this point: F = (XRDLEAD + XRDACTIVE –2) t_c(XTIM)
Figure 6-27. Example Read With Asynchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD XRDACTIVE XRDTRAIL USEREADY
X2TIMING
≥1
3
≥1
1
0
XWRLEAD
N/A ⁽¹⁾
(1) N/A = “Don’t care” for this example
XWRACTIVE
N/A ⁽¹⁾
XWRTRAIL
N/A ⁽¹⁾
READYMODE
1 = XREADY
(Async)
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Electrical Specifications 139